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1. (WO2019064906) METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
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Pub. No.: WO/2019/064906 International Application No.: PCT/JP2018/028793
Publication Date: 04.04.2019 International Filing Date: 01.08.2018
IPC:
B81C 1/00 (2006.01) ,G01F 1/692 (2006.01) ,H01L 21/308 (2006.01)
B PERFORMING OPERATIONS; TRANSPORTING
81
MICRO-STRUCTURAL TECHNOLOGY
C
PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICRO-STRUCTURAL DEVICES OR SYSTEMS
1
Manufacture or treatment of devices or systems in or on a substrate
G PHYSICS
01
MEASURING; TESTING
F
MEASURING VOLUME, VOLUME FLOW, MASS FLOW, OR LIQUID LEVEL; METERING BY VOLUME
1
Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through the meter in a continuous flow
68
by using thermal effects
684
Structural arrangements; Mounting of elements, e.g. in relation to fluid flow
688
using a particular type of heating, cooling or sensing element
69
of resistive type
692
Thin-film arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306
Chemical or electrical treatment, e.g. electrolytic etching
308
using masks
Applicants:
日立オートモティブシステムズ株式会社 HITACHI AUTOMOTIVE SYSTEMS, LTD. [JP/JP]; 茨城県ひたちなか市高場2520番地 2520, Takaba, Hitachinaka-shi, Ibaraki 3128503, JP
Inventors:
土持 秀太郎 TSUCHIMOCHI Shutaro; JP
丹波 栄策 TAMBA Eisaku; JP
池尾 聡 IKEO Satoshi; JP
Agent:
戸田 裕二 TODA Yuji; JP
Priority Data:
2017-18780228.09.2017JP
Title (EN) METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
(FR) PROCÉDÉ DE FABRICATION DE DISPOSITIF À SEMICONDUCTEUR
(JA) 半導体デバイスの製造方法
Abstract:
(EN) In relation to techniques for manufacturing semiconductor devices having an ultrathin diaphragm, the present invention provides a manufacturing method that contributes to an improvement in manufacturing yield and has good workability. This method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device having a diaphragm, and includes a step of forming an electronic circuit element on a top surface of a semiconductor wafer, and a step of forming the diaphragm by etch-removing the reverse surface side of the semiconductor wafer, characterized in that the step of forming the diaphragm includes: a sub-step of affixing onto the top surface of the semiconductor wafer a protective tape obtained by laminating an ultraviolet curing pressure-sensitive adhesive layer onto a resin tape; a sub-step of wet etching the semiconductor wafer from the reverse surface side thereof; a sub-step of irradiating the pressure-sensitive adhesive layer with ultraviolet light; and a sub-step of peeling off the protective tape at a temperature at least equal to the etching temperature of the wet etching and at most equal to the Vicat softening temperature of the resin tape.
(FR) Par rapport à des techniques de fabrication de dispositifs à semi-conducteur ayant un diaphragme ultra-mince, la présente invention concerne un procédé de fabrication qui contribue à une amélioration du rendement de fabrication et a une bonne maniabilité. Ce procédé de fabrication d'un dispositif à semi-conducteur est un procédé de fabrication d'un dispositif à semi-conducteur ayant un diaphragme, et comprend une étape de formation d'un élément de circuit électronique sur une surface supérieure d'une plaquette de semi-conducteur, et une étape de formation du diaphragme par élimination par gravure du côté de surface inverse de la plaquette de semi-conducteur, caractérisé en ce que l'étape de formation du diaphragme comprend : une sous-étape de fixation, sur la surface supérieure de la plaquette de semi-conducteur, d'une bande de protection obtenue par stratification d'une couche adhésive sensible à la pression à durcissement aux ultraviolets sur une bande de résine ; une sous-étape de gravure humide de la plaquette de semi-conducteur du côté de surface inverse de celle-ci ; une sous-étape d'exposition de la couche adhésive sensible à la pression à une lumière ultraviolette ; et une sous-étape de décollement de la bande de protection à une température au moins égale à la température de gravure de la gravure humide et au plus égale à la température de ramollissement Vicat de la bande de résine.
(JA) 極薄ダイアフラムを有する半導体デバイスの製造技術において、製造歩留まりの向上に貢献しかつ高い作業容易性を有する製造方法を提供する。 本発明に係る半導体デバイスの製造方法は、ダイアフラムを有する半導体デバイスを製造する方法であって、半導体ウエハの一表面の上に電子回路要素を形成する工程と、前記半導体ウエハの裏面側をエッチング除去して前記ダイアフラムを形成する工程とを有し、前記ダイアフラムを形成する工程は、樹脂テープ上に紫外線硬化型粘着剤層が積層された保護テープを前記半導体ウエハの表面の上に貼り付ける素工程と、前記半導体ウエハを裏面側からウェットエッチングする素工程と、前記粘着剤層に紫外線を照射する素工程と、前記ウェットエッチングのエッチング温度以上かつ前記樹脂テープのビカット軟化温度以下の温度で前記保護テープを剥離する素工程と、を有することを特徴とする。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)