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1. (WO2019064775) SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/064775 International Application No.: PCT/JP2018/025007
Publication Date: 04.04.2019 International Filing Date: 02.07.2018
IPC:
H01L 25/07 (2006.01) ,H01L 23/12 (2006.01) ,H01L 23/36 (2006.01) ,H01L 25/18 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
36
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
Applicants:
日立金属株式会社 HITACHI METALS, LTD. [JP/JP]; 東京都港区港南一丁目2番70号 2-70, Konan 1-chome, Minato-ku, Tokyo 1088224, JP
Inventors:
谷江 尚史 TANIE Hisashi; JP
島津 ひろみ SHIMAZU Hiromi; JP
伊藤 博之 ITO Hiroyuki; JP
Agent:
特許業務法人平木国際特許事務所 HIRAKI & ASSOCIATES; 東京都港区愛宕二丁目5-1 愛宕グリーンヒルズMORIタワー32階 Atago Green Hills MORI Tower 32F, 5-1, Atago 2-chome, Minato-ku, Tokyo 1056232, JP
Priority Data:
2017-18966729.09.2017JP
Title (EN) SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET SON PROCÉDÉ DE PRODUCTION
(JA) 半導体装置およびその製造方法
Abstract:
(EN) The objective of the present invention is to provide a technique that ensures conduction between a gate terminal of a semiconductor switching element and a wiring layer in a semiconductor device formed with a wiring layer inside a ceramic layer. This semiconductor device comprises: a wiring layer that is inside a ceramic layer formed above an insulation layer; and a metal layer for connecting terminals from the semiconductor switching element other than the gate terminal. The wiring layer and the gate terminal from the semiconductor switching element are connected electrically via a connection part formed from a conductive material. The connection part protrudes more than the metal layer toward the semiconductor switching element (see FIG. 1).
(FR) L'objectif de la présente invention est de fournir une technique qui assure la conduction entre une borne de grille d'un élément de commutation à semi-conducteur et une couche de câblage dans un dispositif à semi-conducteur formé avec une couche de câblage à l'intérieur d'une couche de céramique. Ce dispositif à semi-conducteur comprend : une couche de câblage qui est à l'intérieur d'une couche de céramique formée au-dessus d'une couche d'isolation ; et une couche métallique pour connecter des bornes de l'élément de commutation à semi-conducteur autre que la borne de grille. La couche de câblage et la borne de grille de l'élément de commutation à semi-conducteur sont connectées électriquement par l'intermédiaire d'une partie de connexion formée à partir d'un matériau conducteur. La partie de connexion fait saillie plus que la couche métallique vers l'élément de commutation à semi-conducteur (voir FIG. 1).
(JA) 本発明は、セラミックス層のなかに配線層を形成する半導体装置において、半導体スイッチング素子のゲート端子と配線層との間の導通を確実に得ることができる技術を提供することを目的とする。本発明に係る半導体装置は、絶縁層上に形成されたセラミックス層の内部に配線層を有するとともに、半導体スイッチング素子のゲート端子以外の端子を接続する金属層を有しており、前記半導体スイッチング素子のゲート端子と前記配線層は、導電材料によって形成された接続部を介して電気的に接続されており、前記接続部は前記半導体スイッチング素子に向かって前記金属層よりも突出している(図1参照)。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)