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1. (WO2019064215) MATHEMATICAL PROBLEM SOLVING CIRCUIT COMPRISING RESISTIVE ELEMENTS
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Pub. No.: WO/2019/064215 International Application No.: PCT/IB2018/057487
Publication Date: 04.04.2019 International Filing Date: 27.09.2018
IPC:
G06F 17/12 (2006.01) ,G11C 13/00 (2006.01) ,G06G 7/32 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
17
Digital computing or data processing equipment or methods, specially adapted for specific functions
10
Complex mathematical operations
11
for solving equations
12
Simultaneous equations
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
13
Digital stores characterised by the use of storage elements not covered by groups G11C11/, G11C23/, or G11C25/173
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
G
ANALOGUE COMPUTERS
7
Devices in which the computing operation is performed by varying electric or magnetic quantities
12
Arrangements for performing computing operations, e.g. amplifiers specially adapted therefor
32
for solving of equations
Applicants:
POLITECNICO DI MILANO [IT/IT]; Piazza Leonardo da Vinci, 32 20133 Milano, IT
Inventors:
IELMINI, Daniele; IT
SUN, Zhong; IT
PEDRETTI, Giacomo; IT
Agent:
POSTIGLIONE, Ferruccio; IT
MAZZOCCHI, Stefano; IT
TANA, Maria Gabriella; IT
Priority Data:
10201700010828127.09.2017IT
Title (EN) MATHEMATICAL PROBLEM SOLVING CIRCUIT COMPRISING RESISTIVE ELEMENTS
(FR) CIRCUIT DE RÉSOLUTION DE PROBLÈME MATHÉMATIQUE COMPRENANT DES ÉLÉMENTS RÉSISTIFS
Abstract:
(EN) It is described a mathematical solving circuit (100) comprising: a crosspoint matrix (MG) including a plurality of row conductors (L±), a plurality of column conductors (Cj) and a plurality of analog resistive memories (Gij), each connected between a row conductor and a column conductor; a plurality of operational amplifiers (OA±) each having: a first input terminal (INu) connected to a respective row conductor (Li), a second input terminal (IN2i) connected to a ground terminal (GR) at least one operational amplifier (OAi) of the plurality being such to take the respective first input terminal (INu) to a virtual ground.
(FR) L'invention concerne un circuit de résolution mathématique (100) comprenant : une matrice de points de croisement (MG) comprenant une pluralité de conducteurs en rangées (L ±), une pluralité de conducteurs en colonnes (Cj) et une pluralité de mémoires résistives analogiques (Gij), chacune étant connectée entre un conducteur de rangée et un conducteur de colonne; une pluralité d'amplificateurs opérationnels (OA ±) comportant chacun une première borne d'entrée (INu) connectée à un conducteur de rangée respectif (Li), une seconde borne d'entrée (IN2i) connectée à une borne de masse (GR), au moins un amplificateur opérationnel (OAi) de la pluralité d'amplificateurs étant conçu pour amener la première borne d'entrée respective (INu) à une masse virtuelle.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: Italian (IT)