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1. (WO2019063957) METHOD FOR POROSIFYING A MATERIAL AND SEMICONDUCTOR STRUCTURE
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Pub. No.: WO/2019/063957 International Application No.: PCT/GB2017/052895
Publication Date: 04.04.2019 International Filing Date: 27.09.2017
IPC:
H01L 21/3063 (2006.01) ,H01L 33/16 (2010.01) ,C25F 3/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306
Chemical or electrical treatment, e.g. electrolytic etching
3063
Electrolytic etching
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
02
characterised by the semiconductor bodies
16
with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
C CHEMISTRY; METALLURGY
25
ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
F
PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
3
Electrolytic etching or polishing
02
Etching
12
of semiconducting materials
Applicants:
CAMBRIDGE ENTERPRISE LTD [GB/GB]; The Old Schools Trinity Lane Cambridge, Cambridgeshire CB2 1TN, GB
Inventors:
ZHU, Tongtong; GB
OLIVER, Rachel A.; GB
LIU, Yingjun; GB
Agent:
REDDIE & GROSE LLP; The White Chapel Building 10 Whitechapel High Street London, Greater London E1 8QS, GB
Priority Data:
Title (EN) METHOD FOR POROSIFYING A MATERIAL AND SEMICONDUCTOR STRUCTURE
(FR) PROCÉDÉ PERMETTANT DE RENDRE POREUX UN MATÉRIAU ET STRUCTURE À SEMI-CONDUCTEUR
Abstract:
(EN) A method for porosifying a Ill-nitride material in a semiconductor structure is provided, the semiconductor structure comprising a sub-surface structure of a first Ill-nitride material, having a charge carrier density greater than 5 x 1017 cm-3, beneath a surface layer of a second Ill-nitride material, having a charge carrier density of between 1 x 1014 cm-3 and 1 x 1017 cm-3. The method comprises the steps of exposing the surface layer to an electrolyte, and applying a potential difference between the first Ill-nitride material and the electrolyte, so that the sub-surface structure is porosified by electrochemical etching, while the surface layer is not porosified. A semiconductor structure and uses thereof are further provided.
(FR) La présente invention concerne un procédé permettant de rendre poreux un matériau de nitrure III d'une structure à semi-conducteur, la structure à semi-conducteur comprenant une structure de sous-surface en premier matériau de nitrure III affichant une densité de porteurs de charge supérieure à 5 x 1017 cm-3, située sous une couche d'un second matériau de nitrure III affichant une densité de porteurs de charge s'inscrivant dans une plage de 1 x 1014 cm-3 à 1 x 1017 cm-3. Le procédé comprend les étapes consistant à exposer la couche de surface à un électrolyte, et à appliquer une différence de potentiel entre le premier matériau de nitrure III et l'électrolyte, de sorte que la structure de sous-surface soit rendue poreuse par gravure électrochimique, tout en ne rendant pas poreuse la couche de surface. La présente invention concerne en outre une structure à semi-conducteur et ses utilisations.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)