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1. (WO2019063771) GALVANIC ISOLATED DEVICE AND CORRESPONDING SYSTEM
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/063771 International Application No.: PCT/EP2018/076419
Publication Date: 04.04.2019 International Filing Date: 28.09.2018
IPC:
H03K 19/0175 (2006.01) ,H04B 10/80 (2013.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
19
Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
0175
Coupling arrangements; Interface arrangements
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
B
TRANSMISSION
10
Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
80
Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups H04B10/03-H04B10/70166
Applicants:
INTERDIGITAL CE PATENT HOLDINGS [FR/FR]; 3 rue du colonel Moll 75017 Paris, FR
Inventors:
MARCHAND, Philippe; FR
FOUQUE, Claude; FR
SALOU, Frédérique; FR
Agent:
HUCHET, Anne; FR
PERROT, Sébastien; FR
LORETTE, Anne; FR
ROLLAND, Sophie; FR
LABELLE, Lilian; FR
MORAIN, David; FR
AMOR, Rim; FR
STAHL, Niclas; FR
Priority Data:
17306294.429.09.2017EP
Title (EN) GALVANIC ISOLATED DEVICE AND CORRESPONDING SYSTEM
(FR) DISPOSITIF ISOLÉ GALVANIQUE ET SYSTÈME CORRESPONDANT
Abstract:
(EN) A device including an optoelectric circuit that is configured to provide galvanic isolation between a first circuit and a second circuit is disclosed. The optoelectric circuit includes at least one non-inverting buffer and a metal semiconductor diode. The at least one non-inverting buffer is positioned between a collector of a phototransistor and an anode of a light emitting diode. The metal semiconductor diode is positioned between the collector of the phototransistor and the at least one non-inverting buffer.
(FR) L'invention concerne un dispositif comprenant un circuit optoélectrique configuré pour assurer une isolation galvanique entre un premier et un deuxième circuit. Le circuit optoélectrique comprend au moins un tampon non inverseur et une diode à semi-conducteur métallique. Ledit tampon non inverseur au moins est positionné entre un collecteur d'un phototransistor et une anode d'une diode électroluminescente. La diode à semi-conducteur métallique est positionnée entre le collecteur du phototransistor et ledit tampon non inverseur au moins.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)