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1. (WO2019063604) PATTERING SEMICONDUCTOR FOR TFT DEVICE
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Pub. No.: WO/2019/063604 International Application No.: PCT/EP2018/076103
Publication Date: 04.04.2019 International Filing Date: 26.09.2018
IPC:
H01L 51/40 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
51
Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
05
specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier
40
Processes or apparatus specially adapted for the manufacture or treatment of such devices or of parts thereof
Applicants:
FLEXENABLE LIMITED [GB/GB]; 34 Cambridge Science Park Milton Road Cambridge CB4 0FX, GB
Inventors:
VANDEKERCKHOVE, Herve; GB
DURY, Joffrey; GB
Agent:
MARC NIGEL EVANS; PAGE WHITE & FARRER Bedford House John Street London Greater London WC1N 2BF, GB
Priority Data:
1715794.229.09.2017GB
Title (EN) PATTERING SEMICONDUCTOR FOR TFT DEVICE
(FR) MODÉLISATION D'UN SEMI-CONDUCTEUR POUR UN DISPOSITIF DE TRANSISTOR TFT
Abstract:
(EN) A technique, comprising: forming, over a substrate (2) comprising at least source and drain conductors (4, 6) for one or more transistor devices, at least a first, semiconductor layer (8) providing one or more semiconductor channels for the one or more transistor devices; forming, over the first layer, a second layer (10) that defines at least part of a gate dielectric for the one or more transistor devices; creating a pattern in the second layer, without depositing any temporary material onto the second layer; and using the pattern in the second layer to pattern the first layer.
(FR) La présente invention concerne une technique, consistant : à former, sur un substrat (2) comprenant au moins des conducteurs de source et de drain (4, 6) pour un ou plusieurs dispositifs de transistor, au moins une première couche semi-conductrice (8) fournissant un ou plusieurs canaux semi-conducteurs pour le ou les dispositifs de transistor ; à former, sur la première couche, une seconde couche (10) qui définit au moins une partie d'un diélectrique de grille pour le ou les dispositifs de transistor ; à créer un motif dans la seconde couche, sans déposer de matériau temporaire sur la seconde couche ; et à utiliser le motif dans la seconde couche pour décorer d'un motif la première couche.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)