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1. (WO2019062738) THIN-FILM TRANSISTOR, ARRAY SUBSTRATE AND DISPLAY APPARATUS
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Pub. No.: WO/2019/062738 International Application No.: PCT/CN2018/107513
Publication Date: 04.04.2019 International Filing Date: 26.09.2018
IPC:
H01L 29/786 (2006.01) ,H01L 29/423 (2006.01) ,H01L 27/12 (2006.01) ,G02F 1/1368 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
423
not carrying the current to be rectified, amplified or switched
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362
Active matrix addressed cells
1368
in which the switching element is a three-electrode device
Applicants:
京东方科技集团股份有限公司 BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; 中国北京市 朝阳区酒仙桥路10号 No.10 Jiuxianqiao Rd. Chaoyang District Beijing 100015, CN
重庆京东方光电科技有限公司 CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; 中国重庆市 北碚区水土高新技术产业园云汉大道7号 No.7 Yunhan Rd., Shuitu Hi-tech Industrial Zone Beibei District Chongqing 400714, CN
Inventors:
王骏 WANG, Jun; CN
黄中浩 HUANG, Zhonghao; CN
赵永亮 ZHAO, Yongliang; CN
林承武 RIM, Seungmoo; CN
Agent:
北京三高永信知识产权代理有限责任公司 BEIJING SAN GAO YONG XIN INTELLECTUAL PROPERTY AGENCY CO., LTD.; 中国北京市 海淀区学院路蓟门里和景园A座1单元102室 A-1-102,He Jing Yuan, Ji Men Li, Xueyuan Road Haidian District Beijing 100088, CN
Priority Data:
201721240582.626.09.2017CN
Title (EN) THIN-FILM TRANSISTOR, ARRAY SUBSTRATE AND DISPLAY APPARATUS
(FR) TRANSISTOR À COUCHES MINCES, SUBSTRAT DE RÉSEAU ET APPAREIL D'AFFICHAGE
(ZH) 薄膜晶体管、阵列基板和显示装置
Abstract:
(EN) A thin-film transistor, an array substrate and a display apparatus. The thin-film transistor comprises a base substrate (100), a gate electrode layer (101), a gate insulation layer (102), an active layer (103) and a source/drain electrode layer (104), wherein the gate electrode layer (101) comprises a first gate electrode layer (1011) and a second gate electrode layer (1012), which is between the first gate electrode layer (1011) and the gate insulation layer (102), and the first gate electrode layer (1011) is a metal layer and the second gate electrode layer (1012) is a doped semiconductor material layer. The gate insulation layer is generally made of a material such as silicon dioxide or silicon nitride; a semiconductor material layer is arranged between the first gate electrode layer and the gate insulation layer; and an interface between a gate electrode and the gate insulation layer in a related design is changed to a semiconductor/SiO(or SiN) interface from a metal/SiO(or SiN) interface, such that the defect density between the gate electrode and the gate insulation layer is reduced, and an interface state is reduced. Additionally, by adjusting the doping amount of a semiconductor at the second gate electrode layer, a threshold voltage of the manufactured TFT can be adjusted.
(FR) La présente invention concerne un transistor à couches minces, un substrat de réseau et un appareil d'affichage. Le transistor à couches minces comprend un substrat de base (100), une couche d'électrode de grille (101), une couche d'isolation de grille (102), une couche active (103) et une couche d'électrode de source/drain (104), la couche d'électrode de grille (101) comprenant une première couche d'électrode de grille (1011) et une seconde couche d'électrode de grille (1012), qui se trouve entre la première couche d'électrode de grille (1011) et la couche d'isolation de grille (102), et la première couche d'électrode de grille (1011) est une couche métallique et la seconde couche d'électrode de grille (1012) est une couche de matériau semi-conducteur dopé. La couche d'isolation de grille est généralement constituée d'un matériau tel que du dioxyde de silicium ou du nitrure de silicium ; une couche de matériau semi-conducteur est disposée entre la première couche d'électrode de grille et la couche d'isolation de grille ; et une interface entre une électrode de grille et la couche d'isolation de grille dans une conception associée est changée en un semi-conducteur/SiO (ou SiN) à partir d'une interface métal/SiO (ou SiN), de telle sorte que la densité de défauts entre l'électrode de grille et la couche d'isolation de grille est réduite, et un état d'interface est réduit. De plus, en ajustant la quantité de dopage d'un semi-conducteur au niveau de la seconde couche d'électrode de grille, une tension de seuil du TFT fabriqué peut être ajustée.
(ZH) 一种薄膜晶体管、阵列基板和显示装置。薄膜晶体管包括衬底基板(100)、栅极层(101)、栅极绝缘层(102)、有源层(103)和源漏极层(104),栅极层(101)包括第一栅极层(1011)、以及在第一栅极层(1011)和栅极绝缘层(102)之间的第二栅极层(1012),第一栅极层(1011)为金属层,第二栅极层(1012)为掺杂的半导体材料层。栅极绝缘层通常为二氧化硅、氮化硅等材料,在第一栅极层和栅极绝缘层之间设置半导体材料层,将相关设计中栅极与栅极绝缘层界面从金属/SiO(或SiN)界面变更为半导体/SiO(或SiN)界面,从而降低了栅极和栅极绝缘层之间的缺陷密度,降低了界面态。另外,通过调整第二栅极层的半导体的掺杂量,可以调整制作出的TFT的阈值电压。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)