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1. (WO2019062260) THIN-FILM TRANSISTOR AND METHOD FOR MANUFACTURING SAME, ARRAY SUBSTRATE, AND DISPLAY DEVICE
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/062260 International Application No.: PCT/CN2018/094790
Publication Date: 04.04.2019 International Filing Date: 06.07.2018
IPC:
H01L 29/786 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants:
信利(惠州)智能显示有限公司 TRULY (HUIZHOU) SMART DISPLAY LIMITED [CN/CN]; 中国广东省惠州市 仲恺高新区新华大道南1号 No. 1 South Section of Xinhua Avenue Zhongkai High-Tech Industial Development Zone Huizhou, Guangdong 516029, CN
Inventors:
铃木浩司 SUZUKI, Koji; CN
陈卓 CHEN, Zhuo; CN
张毅先 ZHANG, Yixian; CN
张帆 ZHANG, Fan; CN
任思雨 REN, Siyu; CN
苏君海 SU, Junhai; CN
李建华 LI, Jianhua; CN
Agent:
广州华进联合专利商标代理有限公司 ADVANCE CHINA IP LAW OFFICE; 中国广东省广州市天河区珠江东路6号4501房 (部位:自编01-03和08-12单元)(仅限办公用途) Room 4501, No. 6 Zhujiang East Road, Tianhe District, Guangzhou Guangdong 510623, CN
Priority Data:
201710898220.428.09.2017CN
Title (EN) THIN-FILM TRANSISTOR AND METHOD FOR MANUFACTURING SAME, ARRAY SUBSTRATE, AND DISPLAY DEVICE
(FR) TRANSISTOR À COUCHES MINCES ET SON PROCÉDÉ DE FABRICATION, SUBSTRAT DE RÉSEAU, ET DISPOSITIF D'AFFICHAGE
(ZH) 薄膜晶体管及其制作方法、以及阵列基板与显示装置
Abstract:
(EN) Disclosed in the present invention are a method for manufacturing a thin-film transistor, an array substrate, and a display device. The method for manufacturing a thin-film transistor comprises: forming a buffer layer on a substrate; forming a polysilicon layer on the buffer layer; performing a patterning process on the polysilicon layer to form an active layer; depositing a gate insulating layer on the active layer; depositing a gate metal layer on the gate insulating layer, and performing dry etching on the gate metal layer by means of a patterning process and by using a gas containing CO as an etching gas, to form a gate; performing ion implantation on the active layer by using the gate as a mask to form a source region and a drain region; and depositing a passivation layer on the gate, forming through holes in the gate insulating layer and the passivation layer, and forming a source and a drain.
(FR) La présente invention concerne un procédé de fabrication d'un transistor à couches minces, un substrat de réseau, et un dispositif d'affichage. Le procédé de fabrication d'un transistor à couches minces consiste : à former une couche tampon sur un substrat ; à former une couche de polysilicium sur la couche tampon ; à réaliser un processus de formation de motifs sur la couche de polysilicium pour former une couche active ; à déposer une couche d'isolation de grille sur la couche active ; à déposer une couche de métal de grille sur la couche d'isolation de grille, et à réaliser une gravure sèche sur la couche de métal de grille au moyen d'un processus de formation de motifs et à l'aide d'un gaz contenant du CO en tant que gaz de gravure, pour former une grille ; à réaliser une implantation ionique sur la couche active en utilisant la grille comme masque pour former une région de source et une région de drain ; et à déposer une couche de passivation sur la grille, à former des trous traversants dans la couche d'isolation de grille et la couche de passivation, et à former une source et un drain.
(ZH) 本发明公开了一种薄膜晶体管的制作方法、以及阵列基板与显示装置。上述薄膜晶体管的制作方法包括:在基板上形成缓冲层;在缓冲层上形成多晶硅层;对多晶硅层进行构图工艺,形成有源层;在有源层上沉积栅极绝缘层;在栅极绝缘层上沉积栅极金属层,通过构图工艺,采用含有CO的气体作为刻蚀气体对栅极金属层进行干法刻蚀,形成栅极;以栅极为掩膜,对有源层进行离子注入,形成源区和漏区;在栅极上沉积钝化层,并在栅极绝缘层及钝化层形成过孔,并制作源极及漏极。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)