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1. (WO2019062241) WAFER-LEVEL SYSTEM PACKAGING METHOD AND PACKAGING STRUCTURE
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Pub. No.: WO/2019/062241 International Application No.: PCT/CN2018/093770
Publication Date: 04.04.2019 International Filing Date: 29.06.2018
IPC:
H01L 21/56 (2006.01) ,H01L 21/60 (2006.01) ,H01L 23/498 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56
Encapsulations, e.g. encapsulating layers, coatings
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
Applicants:
中芯集成电路(宁波)有限公司 NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION [CN/CN]; 中国浙江省宁波市 北仑区小港街道安居路335号3幢、4幢、5幢 Building 3, Building 4 And Building 5, 335 Anju Road, Xiaogang Street, Beilun District Ningbo, Zhejiang 315800, CN
Inventors:
刘孟彬 LIU, Mengbin; CN
Agent:
北京市磐华律师事务所 P. C. & ASSOCIATES; 中国北京市 朝阳区建国门外大街22号赛特大厦901-902室 Room 901-902, Scitech Tower, No.22 Jian Guo Men Wai Avenue, Chao Yang District Beijing 100004, CN
Priority Data:
201710917071.130.09.2017CN
201710919199.130.09.2017CN
201810070261.924.01.2018CN
Title (EN) WAFER-LEVEL SYSTEM PACKAGING METHOD AND PACKAGING STRUCTURE
(FR) PROCÉDÉ D'EMBALLAGE DE SYSTÈME AU NIVEAU DE LA TRANCHE ET STRUCTURE D'EMBALLAGE
(ZH) 一种晶圆级系统封装方法以及封装结构
Abstract:
(EN) A wafer-level system packaging method and a packaging structure, the packaging method being used to stack and join at least two wafers (100, 200), in which chips are formed (101, 201), along a vertical stacking direction, comprising: joining two wafers needing to be joined together; after joining, forming plugs (1021, 1022) which are electrically connected to the chips in the two wafers. The wafer-level system packaging method uses wafer-level packaging and system packaging methods in combination, has the advantage of simultaneously integrating multiple chips and completing packaging fabrication on the wafers, and has the advantages of greatly reducing the area of a packaging structure, lowering fabrication costs, optimizing electrical performance, and batch fabrication, while being capable of significantly reducing workload and equipment requirements, and increasing the efficiency and yield of packaging. The packaging structure obtained by means of the wafer-level system packaging method likewise has better performance and higher yield.
(FR) La présente invention concerne un procédé d'emballage de système au niveau de la tranche et une structure d'emballage, le procédé d'emballage étant destiné à empiler et assembler au moins deux tranches (100, 200), dans lesquelles des puces sont formées (101, 201), le long d'une direction d'empilement verticale, consistant : à assembler deux tranches devant être assemblées ; après assemblage, à former des prises (1021, 1022) qui sont électriquement connectées aux puces dans les deux tranches. Le procédé d'emballage de système au niveau de la tranche utilise des procédés d'emballage de système et d'emballage au niveau de la tranche en combinaison, présente l'avantage d'intégrer simultanément de multiples puces et d'achever la fabrication d'emballage sur les tranches, et présente les avantages de réduire considérablement la surface d'une structure d'emballage, d'abaisser les coûts de fabrication, d'optimiser les performances électriques et la fabrication par lots, tout en permettant de réduire de manière significative la charge de travail et le matériel nécessaire, et d'augmenter l'efficacité et le rendement de l'emballage. La structure d'emballage obtenue au moyen du procédé d'emballage de système au niveau de la tranche présente également une meilleure performance et un rendement plus élevé.
(ZH) 一种晶圆级系统封装方法以及封装结构,封装方法用于将至少两片形成有芯片(101,201)的晶圆(100,200)沿上下堆叠的方向,堆叠接合在一起,包括:将需要接合在一起的两片晶圆相接合;在接合之后,形成插塞(1021,1022),与两片晶圆中的芯片电连接。该晶圆级系统封装方法,使用晶圆级封装和系统封装方法相结合,同时实现了多种芯片的集成和在晶圆上完成封装制造的优势,具有大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势,可明显的降低工作量与设备的需求,提高了封装的效率和良率。由该晶圆级系统封装方法制备获得的封装结构同样具有更高的性能和良率。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)