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1. (WO2019062240) WAFER-LEVEL SYSTEM PACKAGE STRUCTURE AND ELECTRONIC DEVICE
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Pub. No.: WO/2019/062240 International Application No.: PCT/CN2018/093769
Publication Date: 04.04.2019 International Filing Date: 29.06.2018
IPC:
H01L 23/31 (2006.01) ,H01L 21/50 (2006.01) ,H01L 21/56 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
31
characterised by the arrangement
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56
Encapsulations, e.g. encapsulating layers, coatings
Applicants:
中芯集成电路(宁波)有限公司 NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION [CN/CN]; 中国浙江省宁波市 北仑区小港街道安居路335号3幢、4幢、5幢 Building 3, Building 4 And Building 5, 335 Anju Road, Xiaogang Street, Beilun District Ningbo, Zhejiang 315800, CN
Inventors:
刘孟彬 LIU, Mengbin; CN
Agent:
北京市磐华律师事务所 P. C. & ASSOCIATES; 中国北京市 朝阳区建国门外大街22号赛特大厦901-902室 Room 901-902, Scitech Tower No.22 Jian Guo Men Wai Avenue, Chao Yang District Beijing 100004, CN
Priority Data:
201710917071.130.09.2017CN
201710919199.130.09.2017CN
201810070260.424.01.2018CN
Title (EN) WAFER-LEVEL SYSTEM PACKAGE STRUCTURE AND ELECTRONIC DEVICE
(FR) STRUCTURE DE BOÎTIER DE SYSTÈME SUR TRANCHE ET DISPOSITIF ÉLECTRONIQUE
(ZH) 一种晶圆级系统封装结构和电子装置
Abstract:
(EN) Provided in the present invention are a wafer-level system package structure and an electronic device, comprising: a substrate, formed with multiple first chips, the first chips grown by using semiconductor processing; and a package layer, embedded with multiple second chips, the package layer covering the substrate and the first chips. At least one second chip is electrically connected to at least one first chip by means of a conductive bump, and the first chip and the second chip which are in electric connection have an overlapping part. According to the wafer-level system package structure of the present invention, the wafer-level package and a system integration method are combined to obtain the advantages of multiple chips being integrated and package fabrication being completed on the substrate.
(FR) La présente invention concerne une structure de boîtier de système sur tranche et un dispositif électronique, comprenant : un substrat, formé avec de multiples premières puces, les premières puces cultivées à l'aide d'un traitement de semi-conducteurs ; et une couche d'encapsulation, intégrée à de multiples secondes puces, la couche d'encapsulation recouvrant le substrat et les premières puces. Au moins une seconde puce est électroconnectée à au moins une première puce au moyen d'une bosse conductrice, et la première puce et la seconde puce qui sont en connexion électrique ont une partie de chevauchement Selon la structure de boîtier de système sur tranche de la présente invention, le boîtier sur tranche et un procédé d'intégration de système sont combinés pour obtenir les avantages de multiples puces qui sont intégrées et la fabrication de boîtier est achevée sur le substrat.
(ZH) 本发明提供一种晶圆级系统封装结构和电子装置,包括:形成有多个第一芯片的衬底,所述第一芯片利用半导体工艺生长而成;内嵌有多个第二芯片的封装层,所述封装层覆盖所述衬底和所述第一芯片;至少其中一个所述第二芯片与至少其中一个所述第一芯片通过导电凸块电连接,电连接的第一芯片和第二芯片具有重叠部分。根据本发明的晶圆级系统封装结构,使晶圆级封装与系统集成方法相结合,同时实现了多种芯片的集成和在衬底上完成封装制造优势。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)