Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2019062238) WAFER LEVEL SYSTEM PACKAGING METHOD AND PACKAGE STRUCTURE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/062238 International Application No.: PCT/CN2018/093684
Publication Date: 04.04.2019 International Filing Date: 29.06.2018
IPC:
H01L 23/498 (2006.01) ,H01L 25/00 (2006.01) ,H01L 21/60 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
Applicants:
中芯集成电路(宁波)有限公司 NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION [CN/CN]; 中国浙江省宁波市 北仑区小港街道安居路335号3幢、4幢、5幢 Building 3, Building 4 and Building 5, 335 Anju Road, Xiaogang Street, Beilun District Ningbo, Zhejiang 315800, CN
Inventors:
刘孟彬 LIU, Mengbin; CN
Agent:
北京市磐华律师事务所 P. C. & ASSOCIATES; 中国北京市 朝阳区建国门外大街22号赛特大厦901-902室 Room 901-902, Scitech Tower No.22 Jian Guo Men Wai Avenue Chao Yang District Beijing 100004, CN
Priority Data:
201710917071.130.09.2017CN
201710919199.130.09.2017CN
201810070263.824.01.2018CN
Title (EN) WAFER LEVEL SYSTEM PACKAGING METHOD AND PACKAGE STRUCTURE
(FR) PROCÉDÉ D'ENCAPSULATION DE SYSTÈME DE NIVEAU DE TRANCHE ET STRUCTURE D'ENCAPSULATION
(ZH) 一种晶圆级系统封装方法以及封装结构
Abstract:
(EN) Provided in the invention are a wafer level system packaging method and package structure. The package structure comprises: forming a substrate having a plurality of first chips, the first chips being grown using a semiconductor process; and embedding a package layer having a plurality of second chips, the package layer covering the substrate and the first chips; wherein at least one of the second chips is electrically connected to at least one of the first chips, and the first chips and the second chips are mutually staggered and electrically connected by an electrical connection structure. The wafer level system packaging method of the present invention combines wafer level packaging and system packaging methods, and has the advantage of simultaneous integration of various chips and completing packaging on a wafer.
(FR) L'invention porte sur un procédé d'encapsulation de système de niveau de tranche et sur une structure d'encapsulation. La structure d'encapsulation comprend : la formation d'un substrat comportant une pluralité de premières puces, les premières puces étant développées à l'aide d'un processus semi-conducteur ; et l'incorporation d'une couche d'encapsulation comportant une pluralité de secondes puces, la couche d'encapsulation recouvrant le substrat et les premières puces, au moins une des secondes puces étant électriquement connectée à au moins une puce parmi les premières puces, et les premières et secondes puces étant mutuellement décalées et électriquement connectées au moyen d'une structure de connexion électrique. Le procédé d'encapsulation de système de niveau de tranche de la présente invention combine des procédés d'encapsulation de niveau de tranche et d'encapsulation de système, et présente l'avantage d'une intégration simultanée de diverses puces et d'achever une encapsulation sur une tranche.
(ZH) 本发明提供一种晶圆级系统封装方法以及封装结构,所述封装结构包括:形成有多个第一芯片的衬底,所述第一芯片利用半导体工艺生长而成;内嵌有多个第二芯片的封装层,所述封装层覆盖所述衬底和所述第一芯片;至少其中一个所述第二芯片与至少其中一个所述第一芯片电连接,所述第一芯片和所述第二芯片相互错开,通过电连接结构电连接。本发明的晶圆级系统封装方法,使用晶圆级封装和系统封装方法相结合,同时实现了多种芯片的集成和在晶圆上完成封装制造的优势。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)