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1. (WO2019061813) ESL-TYPE TFT SUBSTRATE AND MANUFACTURING METHOD THEREFOR
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/061813 International Application No.: PCT/CN2017/114428
Publication Date: 04.04.2019 International Filing Date: 04.12.2017
IPC:
H01L 27/12 (2006.01) ,H01L 21/77 (2017.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
Applicants:
深圳市华星光电半导体显示技术有限公司 SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD. [CN/CN]; 中国广东省深圳市 光明新区公明街道塘明大道9-2号 No. 9-2, Tangming Road, Gongming Street Guangming New District Shenzhen, Guangdong 518132, CN
Inventors:
石龙强 SHI, Longqiang; CN
Agent:
深圳市德力知识产权代理事务所 COMIPS INTELLECTUAL PROPERTY OFFICE; 中国广东省深圳市 福田区上步中路深勘大厦15E Room 15E, Shenkan Building Shangbu Zhong Road, Futian District Shenzhen, Guangdong 518028, CN
Priority Data:
201710900781.328.09.2017CN
Title (EN) ESL-TYPE TFT SUBSTRATE AND MANUFACTURING METHOD THEREFOR
(FR) SUBSTRAT TFT DU TYPE ESL ET SON PROCÉDÉ DE FABRICATION
(ZH) ESL型TFT基板及其制作方法
Abstract:
(EN) Provided are an ESL-type TFT substrate and a manufacturing method therefor. According to the ESL-type TFT substrate, conducted regions subjected to plasma doping are formed on two sides of an active layer (20), and the distance between the two regions, i.e., the width (L0) of a channel region (203) is less than the distance (L1) between a source electrode (41) and a drain electrode (42), so that a relatively small actual channel length is provided, and current increase of the source electrode (41) and the drain electrode (42) can be facilitated, and the problem of small current of the source electrode (41) and the drain electrode (42) of an existing ESL-type TFT substrate can be solved. The method for manufacturing the ESL-type TFT substrate comprises: performing plasma doping on regions on two sides of an active layer (20) to form conducted regions, and setting the distance between the two regions, i.e., the width (L0) of a channel region (203) to be less than the distance (L1) between a source electrode (41) and a drain electrode (42), so that the actual channel length of TFT can be reduced, the current increase of the source electrode (41) and the drain electrode (42) can be facilitated, and the problem of small current of the source electrode (41) and the drain electrode (42) of an existing ESL-type TFT substrate can be solved.
(FR) La présente invention concerne un substrat TFT du type ESL et son procédé de fabrication. Selon le substrat TFT du type ESL, des régions conduites soumises à un dopage par plasma sont formées sur deux côtés d'une couche active (20), et la distance entre les deux régions, c'est-à-dire la largeur (L0) d'une région de canal (203) est inférieure à la distance (L1) entre une électrode de source (41) et une électrode de drain (42), de telle sorte qu'une longueur de canal réelle relativement petite est fournie, et une augmentation de courant de l'électrode de source (41) et de l'électrode de drain (42) peut être facilitée, et le problème de faible courant de l'électrode de source (41) et de L'électrode de drain (42) d'un substrat de TFT du type ESL existant peut être résolu. Le procédé de fabrication du substrat TFT du Type ESL consiste à : réaliser un dopage par plasma sur des régions sur deux côtés d'une couche active (20) pour former des régions conduites, et régler la distance entre les deux régions, c'est-à-dire que la largeur (L0) d'une région de canal (203) est inférieure à la distance (L1) entre une électrode de source (41) et une électrode de drain (42), de telle sorte que la longueur de canal réelle du TFT peut être réduite, l'augmentation de courant de l'électrode de source (41) et l'électrode de drain (42) peut être facilitée, et le problème de faible courant de l'électrode de source (41) et de L'électrode de drain (42) d'un substrat TFT du type ESL existant peut être résolu.
(ZH) 提供一种ESL型TFT基板及其制作方法。ESL型TFT基板,有源层(20)的两侧区域为经等离子掺杂处理而导体化的区域,且该两侧区域之间的距离即沟道区(203)的宽度(L0)小于源漏极(41)、(42)之间的距离(L1),从而具有较小的实际沟道长度,利于源漏极(41)、(42)电流的提高,解决了现有ESL型TFT基板源漏极(41)、(42)电流小的问题。ESL型TFT基板的制作方法通过对有源层(20)的两侧区域进行等离子掺杂处理而使其成为导体化的区域,并且设置该两侧区域之间的距离即沟道区(203)的宽度(L0)小于源漏极(41)、(42)之间的距离(L1),从而能够减小TFT的实际沟道长度,利于源漏极(41)、(42)电流的提高,解决了现有ESL型TFT基板源漏极(41)、(42)电流小的问题。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)
Also published as:
US20190097063