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1. (WO2019061779) ARRAY SUBSTRATE, MASK PLATE AND METHOD FOR MANUFACTURING ARRAY SUBSTRATE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/061779 International Application No.: PCT/CN2017/112849
Publication Date: 04.04.2019 International Filing Date: 24.11.2017
IPC:
H01L 27/12 (2006.01) ,H01L 29/786 (2006.01) ,H01L 21/77 (2017.01) ,G03F 1/38 (2012.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
G PHYSICS
03
PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
F
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
1
Originals for photomechanical production of textured or patterned surfaces, e.g. masks, photo-masks or reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
38
Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
Applicants:
武汉华星光电技术有限公司 WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD [CN/CN]; 中国湖北省武汉市 武汉东湖开发区高新大道666号生物城C5栋 Building C5, Biolake of Optics Valley, No.666 Gaoxin Avenue, Wuhan East Lake High-tech Development Zone Wuhan, Hubei 430070, CN
Inventors:
刘兴华 LIU, Xinghua; CN
Agent:
广州三环专利商标代理有限公司 SCIHEAD IP LAW FIRM; 中国广东省广州市 越秀区先烈中路80号汇华商贸大厦1508室 Room 1508, Huihua Commercial & Trade Building No. 80, XianLie Zhong Road, Yuexiu District Guangzhou, Guangdong 510070, CN
Priority Data:
201710892062.127.09.2017CN
Title (EN) ARRAY SUBSTRATE, MASK PLATE AND METHOD FOR MANUFACTURING ARRAY SUBSTRATE
(FR) SUBSTRAT DE RÉSEAU, PLAQUE DE MASQUE ET PROCÉDÉ DE FABRICATION DE SUBSTRAT DE RÉSEAU
(ZH) 一种阵列基板、掩膜板及阵列基板制作方法
Abstract:
(EN) Provided is an array substrate, comprising a substrate (1), a thin film transistor layer provided on the substrate (1), and a planarization layer (5) provided above the thin film transistor layer. Bumps (51) are formed on the surface of one side, away from the thin film transistor layer, of the planarization layer (5). By means of providing the bumps (51) and by forming a diffuse reflection layer by means of the bumps (51) on the surface of the planarization layer (5), the light reflection phenomenon can be weakened and the backlight requirements can be reduced. Further provided are a mask plate and a method for manufacturing an array substrate using the mask plate.
(FR) L'invention concerne un substrat de réseau, comprenant un substrat (1), une couche de transistor à couches minces disposée sur le substrat (1), et une couche de planarisation (5) disposée au-dessus de la couche de transistor à couches minces. Des bosses (51) sont formées sur la surface d'un côté, à l'opposé de la couche de transistor à couches minces, de la couche de planarisation (5). Au moyen des bosses (51) et en formant une couche de réflexion diffuse au moyen des bosses (51) sur la surface de la couche de planarisation (5), le phénomène de réflexion de lumière peut être affaibli et les exigences de rétroéclairage peuvent être réduites. L'invention concerne en outre une plaque de masque et un procédé de fabrication de substrat utilisant la plaque de masque.
(ZH) 提供一种阵列基板,包括基板(1)、设置基板(1)上的薄膜晶体管层以及设于薄膜晶体管层上方的平坦层(5);平坦层(5)远离薄膜晶体管层的一侧表面形成有凸点(51)。通过设置凸点(51),通过平坦层(5)表面的凸点(51)形成漫反射层,可以弱化反光现象和降低背光需求。还提供一种掩膜板以及利用该掩膜板来制备阵列基板的方法。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)