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1. (WO2019061751) MANUFACTURING METHOD OF TFT ARRAY SUBSTRATE AND STRUCTURE OF TFT ARRAY SUBSTRATE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/061751 International Application No.: PCT/CN2017/111963
Publication Date: 04.04.2019 International Filing Date: 20.11.2017
IPC:
H01L 21/77 (2017.01) ,G02F 1/1362 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362
Active matrix addressed cells
Applicants:
深圳市华星光电半导体显示技术有限公司 SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD. [CN/CN]; 中国广东省深圳市 光明新区公明街道塘明大道9-2号 No.9-2, Tangming Road Gongming Street, Guangming New District Shenzhen, Guangdong 518132, CN
Inventors:
叶岩溪 YE, Yanxi; CN
Agent:
深圳市德力知识产权代理事务所 COMIPS INTELLECTUAL PROPERTY OFFICE; 中国广东省深圳市 福田区上步中路深勘大厦15E Room 15E, Shenkan Building Shangbu Zhong Road, Futian District Shenzhen, Guangdong 518028, CN
Priority Data:
201710901865.928.09.2017CN
Title (EN) MANUFACTURING METHOD OF TFT ARRAY SUBSTRATE AND STRUCTURE OF TFT ARRAY SUBSTRATE
(FR) PROCÉDÉ DE FABRICATION D'UN SUBSTRAT DE RÉSEAU DE TFT, ET STRUCTURE DE SUBSTRAT DE RÉSEAU DE TFT
(ZH) TFT基板的制作方法及其结构
Abstract:
(EN) A manufacturing method of a TFT array substrate and a structure of the TFT array substrate. The manufacturing method of the TFT array substrate comprises: depositing a black photoresist on a second passivation layer (PV2), and performing patterning; and after a main photo spacer (61), a sub photo spacer (62) and a black matrix (63) have been integrally formed, depositing a transparent electrically-conductive film, and performing patterning to form a pixel electrode (71) and a common electrode (72). Since the integrally formed main photo spacer (61), sub photo spacer (62) and black matrix (63) fill in and cover a recess formed after a color resist has been removed from a region where the black matrix (63) is located, the black matrix (63) on which the pixel electrode (71) and the common electrode (72) are formed is flatter, thereby preventing a problem in which an excessively steep edge slope of a color resist results in generation of residues of an electrically-conductive film after etching, and preventing short circuits of the pixel electrode (71) and the common electrode (72).
(FR) La présente invention concerne un procédé de fabrication d'un substrat de réseau de TFT et une structure de substrat de réseau de TFT. Le procédé de fabrication du substrat de réseau de TFT consiste : à déposer une résine photosensible noire sur une seconde couche de passivation (PV2), et à former un motif ; et après formation d'un seul tenant d'un photo-espaceur principal (61), d'un sous-photo-espaceur (62) et d'une matrice noire (63), à déposer un film électroconducteur transparent, et à former un motif de façon à former une électrode pixel (71) et une électrode commune (72). Étant donné que le photo-espaceur principal (61), le sous-photo-espaceur (62) et la matrice noire formés d'un seul tenant (63) remplissent et recouvrent un évidement formé après élimination d'une réserve de couleur d'une région où se trouve la matrice noire (63), la matrice noire (63) sur laquelle sont formées l'électrode pixel (71) et l'électrode commune (72) est plus plate, ce qui permet d'empêcher un problème selon lequel une pente de bord excessivement abrupte d'une réserve de couleur entraîne la génération de résidus d'un film électroconducteur après gravure, et d'empêcher des courts-circuits de l'électrode pixel (71) et de l'électrode commune (72).
(ZH) 一种TFT基板的制作方法及其结构。该TFT基板的制作方法在第二钝化层(PV2)上沉积覆盖黑色光阻并进行图案化处理,形成一体式的主光阻间隔物(61)、次光阻间隔物(62)与黑色矩阵(63)之后,再沉积覆盖透明导电薄膜并进行图案化处理,形成像素电极(71)与公共电极(72),由于一体式的主光阻间隔物(61)、次光阻间隔物(62)与黑色矩阵(63)填充、覆盖了黑色矩阵(63)所在区域内的色阻被挖开的空间,使得像素电极(71)与公共电极(72)形成在较平坦的黑色矩阵(63)上,能够避免由于色阻边缘斜坡过陡导致的导电薄膜蚀刻残留的问题,防止像素电极(71)与公共电极(72)短路。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)