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1. (WO2019061586) DISPLAY PANEL, DISPLAY DEVICE AND PREPARATION METHOD OF LOW TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR
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Pub. No.: WO/2019/061586 International Application No.: PCT/CN2017/106736
Publication Date: 04.04.2019 International Filing Date: 18.10.2017
IPC:
H01L 21/336 (2006.01) ,H01L 29/786 (2006.01) ,H01L 27/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
Applicants:
武汉华星光电技术有限公司 WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD [CN/CN]; 中国湖北省武汉市 武汉东湖开发区高新大道666号生物城C5栋 Building C5, Biolake of Optics Valley No.666 Gaoxin Avenue, Wuhan East Lake High-Tech Development Zone Wuhan, Hubei 430000, CN
Inventors:
张嘉伟 ZHANG, Jiawei; CN
Agent:
广州三环专利商标代理有限公司 SCIHEAD IP LAW FIRM; 中国广东省广州市 越秀区先烈中路80号汇华商贸大厦1508室 Room 1508, Huihua Commercial & Trade Building No.80, Xian Lie Zhong Road, Yuexiu District Guangzhou, Guangdong 510070, CN
Priority Data:
201710883918.926.09.2017CN
Title (EN) DISPLAY PANEL, DISPLAY DEVICE AND PREPARATION METHOD OF LOW TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR
(FR) PANNEAU D'AFFICHAGE, DISPOSITIF D'AFFICHAGE ET PROCÉDÉ DE PRÉPARATION D'UN TRANSISTOR EN COUCHES MINCES DE POLYSILICIUM BASSE TEMPÉRATURE
(ZH) 显示面板、显示装置及低温多晶硅薄膜晶体管的制备方法
Abstract:
(EN) The invention provides a display panel, a display device and a preparation method of a low temperature poly-silicon thin film transistor (LTPS-TFT). The preparation method comprises: providing a base substrate; forming a semiconductor layer on the base substrate; forming a first insulating layer on the semiconductor layer; forming a first metal layer on the first insulating layer and patterning the first metal layer to obtain a first metal gate layer; forming a second insulating layer on the first metal layer; forming a second metal layer on the second insulating layer and patterning the second metal layer to obtain a second metal gate layer, wherein the first metal gate layer and the second metal gate layer are connected; forming a third insulating layer on the second metal layer; forming a third metal layer on the third insulating layer and patterning the third metal layer to form a source and a drain, wherein the source and the drain are connected to the semiconductor layer. The LTPS technology of the present invention can be applied to the production of large-sized panels.
(FR) L'invention porte sur un panneau d'affichage, sur un dispositif d'affichage et sur un procédé de préparation d'un transistor en couches minces de polysilicium basse température (LTPS-TFT). Le procédé de préparation consiste : à fournir un substrat de base ; à former une couche semi-conductrice sur le substrat de base ; à former une première couche isolante sur la couche semi-conductrice ; à former une première couche métallique sur la première couche isolante puis à former des motifs sur la première couche métallique de façon à obtenir une première couche de grille métallique ; à former une deuxième couche isolante sur la première couche métallique ; à former une deuxième couche métallique sur la deuxième couche isolante puis à former des motifs sur la deuxième couche métallique de façon à obtenir une deuxième couche de grille métallique, les première et deuxième couches de grille métallique étant connectées ; à former une troisième couche isolante sur la deuxième couche métallique ; à former une troisième couche métallique sur la troisième couche isolante puis à former des motifs sur la troisième couche métallique de façon à former une source et un drain, la source et le drain étant connectés à la couche semi-conductrice. La technologie LTPS de la présente invention peut être appliquée à la production de panneaux de grandes dimensions.
(ZH) 本发明提供一种显示面板、显示装置及低温多晶硅薄膜晶体管制备方法。所述制备方法包括:提供一衬底基板;在衬底基板上形成半导体层;在半导体层上形成第一绝缘层;在第一绝缘层上形成第一金属层,并对第一金属层进行图形化处理,以得到第一金属栅极层;在第一金属层上形成第二绝缘层;在第二绝缘层上形成第二金属层,并对第二金属层进行图形化处理,得到第二金属栅极层,其中,第一金属栅极层和第二金属栅极层连接;在第二金属层上形成第三绝缘层;在第三绝缘层上形成第三金属层,并对第三金属层进行图形化处理,以形成源极和漏极,其中,源极和漏极与半导体层连接。采用本发明可将LTPS技术应用于大尺寸面板生产中。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)