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1. (WO2019061289) ARRAY SUBSTRATE, DISPLAY APPARATUS, AND METHOD OF FABRICATING ARRAY SUBSTRATE
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Pub. No.: WO/2019/061289 International Application No.: PCT/CN2017/104361
Publication Date: 04.04.2019 International Filing Date: 29.09.2017
IPC:
H01L 27/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
Applicants:
BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; No.10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
BEIJING BOE DISPLAY TECHNOLOGY CO., LTD. [CN/CN]; No. 118 Jinghaiyilu, BDA Beijing 100176, CN
Inventors:
QU, Lianjie; CN
CHUN, Xiaogai; CN
GAO, Xue; CN
ZHAO, Hebin; CN
SHI, Guangdong; CN
LIU, Shuai; CN
QI, Yonglian; CN
GUI, Bingqiang; CN
Agent:
TEE & HOWE INTELLECTUAL PROPERTY ATTORNEYS; Yuan CHEN 10th Floor, Tower D, Minsheng Financial Center, 28 Jianguomennei Avenue, Dongcheng District Beijing 100005, CN
Priority Data:
Title (EN) ARRAY SUBSTRATE, DISPLAY APPARATUS, AND METHOD OF FABRICATING ARRAY SUBSTRATE
(FR) SUBSTRAT DE RÉSEAU, APPAREIL D'AFFICHAGE ET PROCÉDÉ DE FABRICATION DE SUBSTRAT DE RÉSEAU
Abstract:
(EN) The present application discloses an array substrate, a display apparatus and a method of fabricating an array substrate. The array substrate has a plurality of first bottom-gate type thin film transistors each of which including a metal oxide active layer and a plurality of second bottom-gate type thin film transistors each of which including a silicon active layer.
(FR) La présente invention concerne un substrat de réseau, un appareil d'affichage et un procédé de fabrication d'un substrat de réseau. Le substrat de réseau comporte une pluralité de premiers transistors à couches minces de type grille inférieure dont chacun comprend une couche active d'oxyde métallique et une pluralité de seconds transistors à couches minces de type grille inférieure dont chacun comprend une couche active en silicium.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)