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1. WO2019059952 - INTEGRATION OF HIGH DENSITY CROSS-POINT MEMORY AND CMOS LOGIC FOR HIGH DENSITY LOW LATENCY ENVM AND EDRAM APPLICATIONS

Publication Number WO/2019/059952
Publication Date 28.03.2019
International Application No. PCT/US2017/053309
International Filing Date 25.09.2017
IPC
H01L 27/092 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
08including only semiconductor components of a single kind
085including field-effect components only
088the components being field-effect transistors with insulated gate
092complementary MIS field-effect transistors
H01L 21/8234 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology
H01L 27/06 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
06including a plurality of individual components in a non-repetitive configuration
CPC
H01L 25/0657
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; ; Multistep manufacturing processes thereof
03all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
04the devices not having separate containers
065the devices being of a type provided for in group H01L27/00
0657Stacked arrangements of devices
H01L 27/092
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
08including only semiconductor components of a single kind
085including field-effect components only
088the components being field-effect transistors with insulated gate
092complementary MIS field-effect transistors
H01L 27/11504
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11502with ferroelectric memory capacitors
11504characterised by the top-view layout
H01L 27/11507
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11502with ferroelectric memory capacitors
11507characterised by the memory core region
H01L 27/2436
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
24including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, ; e.g. resistance switching non-volatile memory structures
2436comprising multi-terminal selection components, e.g. transistors
H01L 27/2463
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
24including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, ; e.g. resistance switching non-volatile memory structures
2463Arrangements comprising multiple bistable or multistable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays, details of the horizontal layout
Applicants
  • INTEL CORPORATION [US]/[US]
Inventors
  • KARPOV, Elijah V.
  • MAJHI, Prashant
  • DOYLE, Brian S.
  • PILLARISETTY, Ravi
  • WANG, Yih
Agents
  • SULLIVAN, Stephen G.
  • BRASK, Justin K.
  • AUYEUNG, Al
  • BERNADICOU, Michael A.
  • BLAIR, Steven R.
  • BLANK, Eric S.
  • COFIELD, Michael A.
  • DANSKIN, Timothy A.
  • HALEVA, Aaron S.
  • MAKI, Nathan R.
  • MARLINK, Jeffrey S.
  • MOORE, Michael S.
  • PARKER, Wesley E.
  • PUGH, Joseph A.
  • RASKIN, Vladimir
  • STRAUSS, Ryan N.
  • WANG, Yuke
  • YATES, Steven D.
  • ROJO, Estiven
Priority Data
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) INTEGRATION OF HIGH DENSITY CROSS-POINT MEMORY AND CMOS LOGIC FOR HIGH DENSITY LOW LATENCY ENVM AND EDRAM APPLICATIONS
(FR) INTÉGRATION D'UNE MÉMOIRE À POINTS DE CROISEMENT À HAUTE DENSITÉ ET D'UNE LOGIQUE CMOS POUR DES APPLICATIONS D'ENVM ET D'EDRAM À FAIBLE LATENCE ET À HAUTE DENSITÉ
Abstract
(EN)
An embedded cross-point memory array is described. In an example, an integrated circuit structure includes a first die including a cross-point memory array comprising separate memory blocks, the memory blocks including orthogonally arranged conductive lines, and memory elements at cross-sections of the conductive lines. A first plurality of sockets is on the first die adjacent to the memory blocks, the first plurality of sockets comprising a first plurality of pads that connect to at least a portion to the conductive lines of the corresponding memory block. A second die includes logic circuitry and a second plurality of sockets comprising a second plurality of pads at least partially aligned with positions of the first plurality of pads on the first die. A top of the first die and a top of the second die face one another, wherein the first plurality of pads are bonded with the second plurality pads to directly connect the cross-point memory array to the logic circuitry.
(FR)
L'invention concerne une matrice mémoire à points de croisement intégrée. Dans un exemple, une structure de circuit intégré comprend une première puce comprenant une matrice mémoire à points de croisement comprenant des blocs de mémoire séparés, les blocs de mémoire comprenant des lignes conductrices disposées orthogonalement, et des éléments de mémoire au niveau de sections transversales des lignes conductrices. Une première pluralité de supports sont disposés sur la première puce adjacente aux blocs de mémoire, la première pluralité de supports comprenant une première pluralité de pastilles qui se connectent à au moins une partie des lignes conductrices du bloc de mémoire correspondant. Une seconde puce comprend des circuits logiques et une seconde pluralité de supports comprenant une seconde pluralité de pastilles au moins partiellement alignés avec les positions de la première pluralité de pastilles sur la première puce. Une partie supérieure de la première puce et une partie supérieure de la seconde puce se font face, la première pluralité de pastilles étant liées à la seconde pluralité de pastilles pour connecter directement la matrice mémoire à points de croisement aux circuits logiques.
Latest bibliographic data on file with the International Bureau