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1. WO2019055182 - SYSTEM AND METHOD FOR IMPLEMENTING CONFIGURABLE CONVOLUTED NEURAL NETWORKS WITH FLASH MEMORIES

Publication Number WO/2019/055182
Publication Date 21.03.2019
International Application No. PCT/US2018/047438
International Filing Date 22.08.2018
IPC
H01L 27/02 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/04 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
H01L 27/07 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
06including a plurality of individual components in a non-repetitive configuration
07the components having an active region in common
H01L 27/11507 2017.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11502with ferroelectric memory capacitors
11507characterised by the memory core region
H01L 27/11517 2017.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
H01L 29/02 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02Semiconductor bodies
CPC
G06N 3/0454
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
04Architectures, e.g. interconnection topology
0454using a combination of multiple neural nets
G06N 3/0481
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
04Architectures, e.g. interconnection topology
0481Non-linear activation functions, e.g. sigmoids, thresholds
G06N 3/061
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
061using biological neurons, e.g. biological neurons connected to an integrated circuit
G06N 3/063
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
063using electronic means
G06N 3/0635
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
063using electronic means
0635using analogue means
G11C 16/0425
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
0408comprising cells containing floating gate transistors
0425comprising cells containing a merged floating gate and select transistor
Applicants
  • SILICON STORAGE TECHNOLOGY, INC. [US]/[US]
Inventors
  • TIWARI, Vipin
  • DO, Nhan
Agents
  • LIMBACH, Alan
Priority Data
16/107,28221.08.2018US
62/558,98415.09.2017US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SYSTEM AND METHOD FOR IMPLEMENTING CONFIGURABLE CONVOLUTED NEURAL NETWORKS WITH FLASH MEMORIES
(FR) SYSTÈME ET PROCÉDÉ DE MISE EN ŒUVRE DE RÉSEAUX NEURONAUX CONVOLUTÉS CONFIGURABLES AVEC DES MÉMOIRES FLASH
Abstract
(EN)
A memory array with memory cells arranged in rows and columns. Each memory cell includes source and drain regions with a channel region there between, a floating gate disposed over a first channel region portion, and a second gate disposed over a second channel region portion. A plurality of bit lines each extends along one of the columns and is electrically connected to the drain regions of a first group of one or more of the memory cells in the column and is electrically isolated from the drain regions of a second group of one or more of the memory cells in the column. A plurality of source lines each is electrically connected to the source regions memory cells in one of the columns or rows. A plurality of gate lines each is electrically connected to the second gates of memory cells in one of the columns or rows.
(FR)
La présente invention concerne une puce de mémoire comprenant des cellules de mémoire agencées en rangées et en colonnes. Chaque cellule de mémoire comprend des régions de source et de drain avec une région de canal entre celles-ci, une grille flottante disposée sur une première partie de région de canal, et une deuxième grille disposée sur une deuxième partie de région de canal. Une pluralité de lignes de bits s'étendent chacune le long de l'une des colonnes et sont électriquement connectées aux régions de drain d'un premier groupe d'une ou plusieurs des cellules de mémoire dans la colonne et sont électriquement isolées des régions de drain d'un deuxième groupe d'une ou plusieurs des cellules de mémoire dans la colonne. Une pluralité de lignes de source sont chacune électriquement connectées aux cellules de mémoire de régions de source dans l'une des colonnes ou rangées. Une pluralité de lignes de grille sont chacune électriquement connectées aux deuxièmes grilles de cellules de mémoire dans l'une des colonnes ou rangées.
Also published as
JP2020515174
Latest bibliographic data on file with the International Bureau