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1. WO2019055100 - REMOTE DIRECT MEMORY ACCESS IN COMPUTING SYSTEMS

Publication Number WO/2019/055100
Publication Date 21.03.2019
International Application No. PCT/US2018/039638
International Filing Date 27.06.2018
IPC
H04L 12/721 2013.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12Data switching networks
70Packet switching systems
701Routing or path finding
721Routing procedures, e.g. shortest path routing, source routing, link state routing or distance vector routing
G06F 15/173 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general; Data processing equipment in general
16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
163Interprocessor communication
173using an interconnection network, e.g. matrix, shuffle, pyramid, star or snowflake
CPC
G06F 15/17331
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
163Interprocessor communication
173using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
17306Intercommunication techniques
17331Distributed shared memory [DSM], e.g. remote direct memory access [RDMA]
G06F 15/76
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
76Architectures of general purpose stored program computers
G06F 2009/45583
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
44Arrangements for executing specific programs
455Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
45533Hypervisors; Virtual machine monitors
45558Hypervisor-specific management and integration aspects
45583Memory management, e.g. access or allocation
G06F 2009/45595
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
44Arrangements for executing specific programs
455Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
45533Hypervisors; Virtual machine monitors
45558Hypervisor-specific management and integration aspects
45595Network integration; Enabling network access in virtual machine instances
G06F 9/45533
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
44Arrangements for executing specific programs
455Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
45533Hypervisors; Virtual machine monitors
G06F 9/45558
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
44Arrangements for executing specific programs
455Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
45533Hypervisors; Virtual machine monitors
45558Hypervisor-specific management and integration aspects
Applicants
  • MICROSOFT TECHNOLOGY LICENSING, LLC [US]/[US]
Inventors
  • KOCHEVAR-CURETON, Alec
  • CHATURMOHTA, Somesh
  • LAM, Norman
  • MUNDKUR, Sambhrama
  • FIRESTONE, Daniel
Agents
  • MINHAS, Sandip S.
  • CHEN, Wei-Chen Nicholas
  • HINOJOSA, Brianna L.
  • HOLMES, Danielle J.
  • SWAIN, Cassandra T.
  • WONG, Thomas S.
  • CHOI, Daniel
  • HWANG, William C.
  • WIGHT, Stephen A.
  • CHATTERJEE, Aaron C.
  • JARDINE, John S.
  • GOLDSMITH, Micah P.
Priority Data
15/824,92528.11.2017US
62/558,82714.09.2017US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) REMOTE DIRECT MEMORY ACCESS IN COMPUTING SYSTEMS
(FR) ACCÈS DIRECT À LA MÉMOIRE À DISTANCE DANS DES SYSTÈMES INFORMATIQUES
Abstract
(EN)
Distributed computing systems, devices, and associated methods of remote direct memory access ("RDMA") packet routing are disclosed herein. In one embodiment, a server includes a main processor, a network interface card ("NIC"), and a field programmable gate array ("FPGA") operatively coupled to the main processor via the NIC. The FPGA includes an inbound processing path having an inbound packet buffer configured to receive an inbound packet from the computer network, a NIC buffer, and a multiplexer between the inbound packet buffer and the NIC, and between the NIC buffer and the NIC. The FPGA also includes an outbound processing path having an outbound action circuit having an input to receive the outbound packet from the NIC, a first output to the computer network, and a second output to the NIC buffer in the inbound processing path.
(FR)
L'invention concerne des systèmes informatiques distribués, des dispositifs et des procédés associés de routage de paquets à accès direct à la mémoire (RDMA) à distance. Dans un mode de réalisation, un serveur comprend un processeur principal, une carte d'interface réseau ("NIC"), et un réseau prédiffusé programmable par l'utilisateur ("FPGA") couplé de manière fonctionnelle au processeur principal par l'intermédiaire de la NIC. Le FPGA comprend un chemin de traitement entrant comportant un tampon de paquets entrant configuré pour recevoir un paquet entrant provenant du réseau informatique, un tampon NIC, et un multiplexeur entre le tampon de paquets entrant et le NIC, et entre le tampon NIC et le NIC. Le FPGA comprend également un chemin de traitement sortant comportant un circuit d'action sortante comportant une entrée pour recevoir le paquet sortant du NIC, une première sortie vers le réseau informatique, et une seconde sortie vers le tampon NIC dans le chemin de traitement entrant.
Also published as
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