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1. WO2019054495 - MEMORY CIRCUIT DEVICE AND METHOD FOR USING SAME

Publication Number WO/2019/054495
Publication Date 21.03.2019
International Application No. PCT/JP2018/034229
International Filing Date 14.09.2018
Chapter 2 Demand Filed 05.02.2019
IPC
G11C 11/16 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
02using magnetic elements
16using elements in which the storage effect is based on magnetic spin effect
G06F 5/10 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
5Methods or arrangements for data conversion without changing the order or content of the data handled
06for changing the speed of data flow, i.e. speed regularising
10having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
G06F 12/00 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
G11C 8/10 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
8Arrangements for selecting an address in a digital store
10Decoders
H03K 19/177 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02using specified components
173using elementary logic circuits as components
177arranged in matrix form
CPC
G06F 12/00
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
G06F 5/10
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
5Methods or arrangements for data conversion without changing the order or content of the data handled
06for changing the speed of data flow, i.e. speed regularising ; or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor;
10having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
G11C 11/161
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
02using magnetic elements
16using elements in which the storage effect is based on magnetic spin effect
161details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
G11C 11/1653
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
02using magnetic elements
16using elements in which the storage effect is based on magnetic spin effect
165Auxiliary circuits
1653Address circuits or decoders
G11C 11/1657
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
02using magnetic elements
16using elements in which the storage effect is based on magnetic spin effect
165Auxiliary circuits
1653Address circuits or decoders
1657Word-line or row circuits
G11C 11/1659
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
02using magnetic elements
16using elements in which the storage effect is based on magnetic spin effect
165Auxiliary circuits
1659Cell access
Applicants
  • 国立大学法人東北大学 TOHOKU UNIVERSITY [JP]/[JP]
Inventors
  • 羽生 貴弘 HANYU Takahiro
  • 鈴木 大輔 SUZUKI Daisuke
  • 大野 英男 OHNO Hideo
  • 遠藤 哲郎 ENDOH Tetsuo
Agents
  • 特許業務法人ドライト国際特許事務所 DORAIT IP LAW FIRM
Priority Data
2017-17824115.09.2017JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) MEMORY CIRCUIT DEVICE AND METHOD FOR USING SAME
(FR) DISPOSITIF DE CIRCUIT DE MÉMOIRE ET SON PROCÉDÉ D'UTILISATION
(JA) メモリ回路デバイス及びその使用方法
Abstract
(EN)
The purpose of the present invention is to provide a memory circuit device that enables the circuit to be downscaled. The memory circuit device is provided with: multiple memory cells 11, each comprising a variable resistance memory component; a write circuit unit 20 for writing data into the memory cells; and a read circuit unit 30 for reading the data written in the memory cells. The device is configured to have: a selection circuit unit 40 which is disposed in common for the write circuit unit 20 and read circuit unit 30 and selects a memory cell to be activated out of the multiple memory cells 11 on the basis of cell designation information; and control circuit parts 14a, 14b, 15 which selectively enables either the write circuit unit 20 to write data into the memory cell selected by the selection circuit unit 40 or the read circuit unit 30 to read data therefrom.
(FR)
Le but de la présente invention est de fournir un dispositif de circuit de mémoire qui permet au circuit d'être réduit à l'échelle. Le dispositif de circuit de mémoire comporte : de multiples cellules de mémoire (11), chacune comprenant un composant de mémoire à résistance variable; une unité de circuit d'écriture (20) pour écrire des données dans les cellules de mémoire; et une unité de circuit de lecture (30) pour lire les données écrites dans les cellules de mémoire. Le dispositif est configuré pour comporter : une unité de circuit de sélection (40) qui est disposée en commun pour l'unité de circuit d'écriture (20) et l'unité de circuit de lecture (30) et sélectionne une cellule de mémoire à activer parmi les multiples cellules de mémoire (11) sur la base d'informations de désignation de cellule; et des parties de circuit de commande (14a, 14b, 15) qui permettent sélectivement soit à l'unité de circuit d'écriture (20) d'écrire des données dans la cellule de mémoire sélectionnée par l'unité de circuit de sélection (40) soit à l'unité de circuit de lecture (30) de lire des données à partir de celle-ci.
(JA)
回路規模をより小さくすることのできるメモリ回路デバイスを提供するものことである。それぞれが抵抗変化型記憶素子により構成された複数のメモリセル11と、メモリセルにデータを書き込む書込み回路部20と、モリセルに書き込まれているデータを読み出す読出し回路部30と、を備えたメモリ回路デバイスであって、書込み回路部20及び読出し回路部30の双方に対して共通に設けられ、セル指定情報に基づいて複数のメモリセル11から有効にすべきメモリセルを選択する選択回路部40と、選択回路部40により選択されたメモリセルに対して、書込み回路部20によるデータの書込み、及び読出し回路部30によるデータの読出しのいずれかを選択的に可能にさせる制御回路部14a,14b、15と、を有する構成となる。
Also published as
Latest bibliographic data on file with the International Bureau