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1. WO2019053925 - SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SUBSTRATE TREATMENT DEVICE, AND PROGRAM

Publication Number WO/2019/053925
Publication Date 21.03.2019
International Application No. PCT/JP2018/009964
International Filing Date 14.03.2018
IPC
H01L 21/31 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
H01L 21/316 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
314Inorganic layers
316composed of oxides or glassy oxides or oxide-based glass
H01L 21/318 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
314Inorganic layers
318composed of nitrides
CPC
H01L 21/31
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
H01L 21/316
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
314Inorganic layers
316composed of oxides or glassy oxides or oxide based glass
H01L 21/318
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
314Inorganic layers
318composed of nitrides
Applicants
  • 株式会社KOKUSAI ELECTRIC KOKUSAI ELECTRIC CORPORATION [JP]/[JP]
Inventors
  • 中山 雅則 NAKAYAMA, Masanori
  • 舟木 克典 FUNAKI, Katsunori
  • 上田 立志 UEDA, Tatsushi
  • 坪田 康寿 TSUBOTA, Yasutoshi
  • 竹島 雄一郎 TAKESHIMA, Yuichiro
  • 井川 博登 IGAWA, Hiroto
  • 寺崎 正 TERASAKI, Tadashi
Priority Data
2017-17454312.09.2017JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SUBSTRATE TREATMENT DEVICE, AND PROGRAM
(FR) PROCÉDÉ DE FABRICATION DE DISPOSITIF À SEMI-CONDUCTEUR, DISPOSITIF DE TRAITEMENT DE SUBSTRAT ET PROGRAMME
(JA) 半導体装置の製造方法、基板処理装置及びプログラム
Abstract
(EN)
This manufacturing method comprises: a step for feeding oxygen gas into a reaction furnace in which the inner wall is at least partially formed from quartz; a step for plasma-exciting the oxygen gas fed into the reaction furnace; a first step for removing, by means of the plasma-excited oxygen gas, hydroxyl groups from an exposed surface of the inner wall formed from quartz and modifying the surface layer of the exposed surface; a step for feeding nitrogen gas into the reaction furnace; a step for plasma-exciting the nitrogen gas fed into the reaction furnace; and a second step for modifying, by means of the plasma-excited nitrogen gas, the surface layer of the exposed surface, which has been modified with the plasma-excited oxygen gas, from a silicon dioxide layer to a silicon nitride layer. This method reduces the generation of particles, etc. resulting from etching of the inner surface of the reaction furnace by use of plasma when treating a substrate through plasma excitation of treatment gases, and thereby improves the quality of semiconductor devices.
(FR)
L'invention concerne un procédé de fabrication comprenant : une étape d'alimentation en oxygène gazeux dans un four de réaction dans lequel la paroi interne est au moins partiellement formée à partir de quartz ; une étape d'excitation par plasma de l'oxygène gazeux introduit dans le four de réaction ; une première étape consistant à éliminer, au moyen de l’oxygène gazeux excité par plasma, des groupes hydroxyle d'une surface exposée de la paroi interne formée à partir de quartz et modifier la couche de surface de la surface exposée ; une étape consistant à introduire de l'azote gazeux dans le four de réaction ; une étape consistant à exciter au plasma l'azote gazeux introduit dans le four de réaction ; et une seconde étape consistant à modifier, au moyen de l'azote gazeux excité par plasma, la couche de surface de la surface exposée, qui a été modifiée avec l'oxygène gazeux excité par plasma, à partir d'une couche de dioxyde de silicium à une couche de nitrure de silicium. Ce procédé réduit la génération de particules, etc. Résultant de la gravure de la surface interne du four de réaction par utilisation de plasma lors du traitement d'un substrat par excitation plasma de gaz de traitement, et améliore ainsi la qualité de dispositifs à semi-conducteur.
(JA)
内側壁の少なくとも一部が石英で構成された反応炉内に酸素ガスを供給する工程と、反応炉内に供給された酸素ガスをプラズマ励起する工程と、プラズマ励起された酸素ガスにより、石英で構成された内側壁の露出面から水酸基を除去するとともに、露出面の表層を改質する第1工程と、反応炉内に窒素ガスを供給する工程と、反応炉内に供給された窒素ガスをプラズマ励起する工程と、プラズマ励起された窒素ガスにより、プラズマ励起された酸素ガスにより改質された露出面の表層を二酸化ケイ素から窒化ケイ素の層に改質する第2工程と、を行う。これにより、処理ガスをプラズマ励起することにより基板を処理する際に、プラズマにより反応炉内面へのエッチングにより生じるパーティクル等の発生を低減し、半導体装置の品質を向上させる。
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