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1. WO2019053840 - ELECTRONIC MODULE AND METHOD FOR MANUFACTURING ELECTRONIC MODULE

Publication Number WO/2019/053840
Publication Date 21.03.2019
International Application No. PCT/JP2017/033267
International Filing Date 14.09.2017
Chapter 2 Demand Filed 21.02.2018
IPC
H05K 3/46 2006.01
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
46Manufacturing multi-layer circuits
H05K 1/02 2006.01
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
CPC
H01L 21/56
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
H01L 21/565
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
565Moulds
H01L 2224/13016
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
12Structure, shape, material or disposition of the bump connectors prior to the connecting process
13of an individual bump connector
13001Core members of the bump connector
1301Shape
13016in side view
H01L 2224/13017
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
12Structure, shape, material or disposition of the bump connectors prior to the connecting process
13of an individual bump connector
13001Core members of the bump connector
1301Shape
13016in side view
13017being non uniform along the bump connector
H01L 2224/16145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16135the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
16145the bodies being stacked
H01L 2224/16227
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16151the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
16221the body and the item being stacked
16225the item being non-metallic, e.g. insulating substrate with or without metallisation
16227the bump connector connecting to a bond pad of the item
Applicants
  • 新電元工業株式会社 SHINDENGEN ELECTRIC MANUFACTURING CO., LTD. [JP]/[JP]
Inventors
  • 松嵜 理 MATSUZAKI Osamu
  • 池田 康亮 IKEDA Kosuke
Agents
  • 大野 聖二 OHNO Seiji
  • 大野 浩之 OHNO Hiroyuki
Priority Data
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) ELECTRONIC MODULE AND METHOD FOR MANUFACTURING ELECTRONIC MODULE
(FR) MODULE ÉLECTRONIQUE ET PROCÉDÉ DE FABRICATION DE MODULE ÉLECTRONIQUE
(JA) 電子モジュール及び電子モジュールの製造方法
Abstract
(EN)
This electronic module has: a first substrate 11; electronic elements 13, 23, which are provided on one side of the first substrate 11; a second substrate 21 that is provided on one side of the electronic elements 13, 23; a first connecting body 210 that is provided between the first substrate 11 and the second substrate 21; a second connecting body 220, which is provided between the first substrate 11 and the second substrate 21, and which has a length that is shorter than that of the first connecting body 210; and a sealing section 90 that seals at least the electronic elements. The first connecting body 210 is not electrically connected to the electronic elements, and the second connecting body 220 is electrically connected to the electronic elements 13, 23.
(FR)
Ce module électronique comprend : un premier substrat (11); des éléments électroniques (13, 23), qui sont disposés sur un côté du premier substrat (11); un second substrat (21) qui est disposé sur un côté des éléments électroniques (13, 23); un premier corps de connexion (210) qui est disposé entre le premier substrat (11) et le second substrat (21); un second corps de connexion (220), qui est disposé entre le premier substrat (11) et le second substrat (21), et qui présente une longueur qui est plus courte que celle du premier corps de connexion (210); et une section d'étanchéité (90) qui assure l'étanchéité d'au moins les éléments électroniques. Le premier corps de connexion (210) n'est pas électriquement connecté aux éléments électroniques, et le second corps de connexion (220) est électriquement connecté aux éléments électroniques (13, 23).
(JA)
電子モジュールは、第一基板11と、前記第一基板11の一方側に設けられた電子素子13,23と、前記電子素子13,23の一方側に設けられた第二基板21と、前記第一基板11と前記第二基板21との間に設けられた第一連結体210と、前記第一基板11と前記第二基板21との間に設けられ、前記第一連結体210よりも長さの短い第二連結体220と、少なくとも前記電子素子を封止する封止部90と、を有する。前記第一連結体210は前記電子素子と電気的に接続されず、前記第二連結体220は前記電子素子13,23と電気的に接続される。
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