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1. WO2019053202 - A METHOD FOR MANUFACTURING A P-DOPED GRID IN AN N-DOPED SIC LAYER

Publication Number WO/2019/053202
Publication Date 21.03.2019
International Application No. PCT/EP2018/074908
International Filing Date 14.09.2018
Chapter 2 Demand Filed 03.07.2019
IPC
H01L 21/329 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
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21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
328Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors
329the devices comprising one or two electrodes, e.g. diodes
H01L 21/337 2006.01
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21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334Multistep processes for the manufacture of devices of the unipolar type
335Field-effect transistors
337with a PN junction gate
H01L 29/808 2006.01
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29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
80with field effect produced by a PN or other rectifying junction gate
808with a PN junction gate
H01L 29/872 2006.01
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29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
86controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861Diodes
872Schottky diodes
H01L 29/739 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
70Bipolar devices
72Transistor-type devices, i.e. able to continuously respond to applied control signals
739controlled by field effect
H01L 29/78 2006.01
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29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
CPC
H01L 21/02167
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21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02107Forming insulating materials on a substrate
02109characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
02112characterised by the material of the layer
02123the material containing silicon
02167the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
H01L 21/02447
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21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02365Forming inorganic semiconducting materials on a substrate
02436Intermediate layers between substrates and deposited layers
02439Materials
02441Group 14 semiconducting materials
02447Silicon carbide
H01L 21/02529
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21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02365Forming inorganic semiconducting materials on a substrate
02518Deposited layers
02521Materials
02524Group 14 semiconducting materials
02529Silicon carbide
H01L 21/02634
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21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02365Forming inorganic semiconducting materials on a substrate
02612Formation types
02617Deposition types
02634Homoepitaxy
H01L 21/26513
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21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
26Bombardment with radiation
263with high-energy radiation
265producing ion implantation
26506in group IV semiconductors
26513of electrically active species
H01L 21/28537
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
283Deposition of conductive or insulating materials for electrodes ; conducting electric current
285from a gas or vapour, e.g. condensation
28506of conductive layers
28512on semiconductor bodies comprising elements of Group IV of the Periodic System
28537Deposition of Schottky electrodes
Applicants
  • ASCATRON AB [SE]/[SE]
Inventors
  • SCHÖNER, Adolf
  • RESHANOV, Sergey
  • THIERRY-JEBALI, Nicolas
  • ELAHIPANAH, Hossein
Agents
  • STRÖM & GULLIKSSON AB
Priority Data
1751138-715.09.2017SE
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) A METHOD FOR MANUFACTURING A P-DOPED GRID IN AN N-DOPED SIC LAYER
(FR) PROCÉDÉ DE FABRICATION D'UNE GRILLE DOPÉE P DANS UNE COUCHE SIC DOPÉE N
Abstract
(EN)
A grid is manufactured with a combination of ion implant and epitaxy growth. The grid structure is made in a SiC semiconductor material with the steps of a) providing a substrate comprising a doped semiconductor SiC material, said substrate comprising a first layer (n1), b) by epitaxial growth adding at least one doped semiconductor SiC material to form separated second regions (p2) on the first layer (n1), if necessary with aid of removing parts of the added semiconductor material to form separated second regions (p2) on the first layer (n1), and c) by ion implantation at least once at a stage selected from the group consisting of directly after step a), and directly after step b); implanting ions in the first layer (n1) to form first regions (p1). It is possible to manufacture a grid with rounded corners as well as an upper part with a high doping level. It is possible to manufacture a component with efficient voltage blocking, high current conduction, low total resistance, high surge current capability, and fast switching.
(FR)
L'invention concerne un procédé de fabrication d'une grille combinant une implantation ionique et une croissance épitaxiale. La structure de grille est faite dans un matériau semi-conducteur SiC par la mise en oeuvre des étapes consistant à : a) fournir un substrat comprenant un matériau SiC semi-conducteur dopé, ledit substrat comprenant une première couche (n1), b) ajouter par croissance épitaxiale au moins un matériau SiC semi-conducteur dopé pour former des secondes régions séparées (p2) sur la première couche (n1), si nécessaire en éliminant des parties du matériau semi-conducteur ajouté pour former des secondes régions séparées (p2) sur la première couche (n1), et c) par implantation ionique, au moins une fois à un stade choisi entre directement après l'étape a) et directement après l'étape b) ; implanter des ions dans la première couche (n1) pour former des premières régions (p1). L'invention permet de fabriquer une grille aux coins arrondis ainsi qu'une partie supérieure présentant un niveau de dopage élevé. L'invention permet de fabriquer un composant à blocage de tension efficace, à conduction électrique élevée, à faible résistance totale, à capacité de courant de surtension élevée et à commutation rapide.
Also published as
JP2020537040
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