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1. (WO2019050848) BI-STABLE STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELLS FORMED FROM III-V COMPOUNDS AND CONFIGURED TO ACHIEVE HIGHER OPERATING SPEEDS
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Pub. No.: WO/2019/050848 International Application No.: PCT/US2018/049371
Publication Date: 14.03.2019 International Filing Date: 04.09.2018
IPC:
H01L 27/108 (2006.01) ,H01L 27/102 (2006.01) ,G11C 11/411 (2006.01) ,H01L 27/11 (2006.01) ,H01L 29/78 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
102
including bipolar components
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
34
using semiconductor devices
40
using transistors
41
forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
411
using bipolar transistors only
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
11
Static random access memory structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
Applicants:
QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors:
TAO, Gengming; US
LI, Xia; US
YANG, Bin; US
Agent:
TERRANOVA, Steven, N.; US
Priority Data:
15/696,63006.09.2017US
Title (EN) BI-STABLE STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELLS FORMED FROM III-V COMPOUNDS AND CONFIGURED TO ACHIEVE HIGHER OPERATING SPEEDS
(FR) CELLULES BINAIRES DE MÉMOIRE VIVE STATIQUE (SRAM) BISTABLES FORMÉES À PARTIR DE COMPOSÉS III-V ET CONFIGURÉES POUR OBTENIR DES VITESSES DE FONCTIONNEMENT PLUS ÉLEVÉES
Abstract:
(EN) Bi-stable static random access memory (SRAM) bit cells formed from III- V compounds and configured to achieve higher operating speeds are disclosed. In one aspect, a bi-stable SRAM bit cell includes substrate (202), a first well layer (204) formed over substrate from a III- V compound doped with a first type material, and a second well layer (206) formed over the first well layer (204) from a lll-V compound doped with a second type material. A channel layer (208) is formed over the second well layer (206) from a lll-V compound doped with the first type material. Source and drain regions (210, 214) are formed over the channel layer (208) from a lll-V compound doped with the first type material, and a gate region (224) is formed over the channel layer (208). Bipolar junction transistors (BJTs, 228(1) and 228(2)) are formed such that a data value can be stored in second well layer (206). A collector tap electrode (CL) is configured to provide access to collector of each BJT for reading or writing data.
(FR) La présente invention concerne des cellules binaires de mémoire vive statique (SRAM) bistables formées à partir de composés III-V et configurées pour obtenir des vitesses de fonctionnement plus élevées. Selon un aspect, une cellule binaire SRAM bistable comprend un substrat (202), une première couche de puits (204) formée sur un substrat à partir d'un composé III-V dopé avec matériau de premier type, et une seconde couche de puits (206) formée sur la première couche de puits (204) à partir d'un composé III-V dopé avec un matériau de second type. Une couche de canal (208) est formée sur la seconde couche de puits (206) à partir d'un composé III-V dopé avec le matériau de premier type. Des régions de source et de drain (210, 214) sont formées sur la couche de canal (208) à partir d'un composé III-V dopé avec le matériau de premier type, et une région de grille (224) est formée sur la couche de canal (208). Des transistors à jonction bipolaire (BJT, 228 (1) et 228 (2)) sont formés de telle sorte qu'une valeur de données peut être stockée dans la seconde couche de puits (206). Une électrode de prise de collecteur (CL) est configurée pour fournir un accès au collecteur de chaque BJT afin de lire ou écrire des données.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)