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1. (WO2019050805) MEMORY ARRAYS COMPRISING VERTICALLY-ALTERNATING TIERS OF INSULATIVE MATERIAL AND MEMORY CELLS AND METHODS OF FORMING A MEMORY ARRAY
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Pub. No.: WO/2019/050805 International Application No.: PCT/US2018/049215
Publication Date: 14.03.2019 International Filing Date: 31.08.2018
IPC:
H01L 27/07 (2006.01) ,H01L 27/02 (2006.01) ,H01L 27/11556 (2017.01) ,H01L 27/11582 (2017.01) ,H01L 27/108 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
06
including a plurality of individual components in a non-repetitive configuration
07
the components having an active region in common
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
[IPC code unknown for ERROR IPC Code incorrect: invalid subgroup (0=>999999)!][IPC code unknown for ERROR IPC Code incorrect: invalid subgroup (0=>999999)!]
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
Applicants:
MICRON TECHNOLOGY, INC. [US/US]; 8000 South Federal Way Boise, ID 83716, US
Inventors:
RAMASWAMY, Durai Vishak, Nirmal; US
Agent:
MATKIN, Mark S.; US
LATWESEN, David, G.; US
HENDRICKSEN, Mark, W.; US
GRZELAK, Keith, D.; US
HYTA, Robert; US
Priority Data:
62/554,97206.09.2017US
Title (EN) MEMORY ARRAYS COMPRISING VERTICALLY-ALTERNATING TIERS OF INSULATIVE MATERIAL AND MEMORY CELLS AND METHODS OF FORMING A MEMORY ARRAY
(FR) BARRETTES DE MÉMOIRE COMPRENANT DES ÉTAGES ALTERNÉS VERTICALEMENT DE MATÉRIAU ISOLANT ET DE CELLULES DE MÉMOIRE ET PROCÉDÉS DE FORMATION D’UNE BARRETTE DE MÉMOIRE
Abstract:
(EN) A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a capacitor. The capacitor comprises a first electrode electrically coupled to a source/drain region of the transistor. The first electrode comprises an annulus in a straight-line horizontal cross-section and a capacitor insulator radially inward of the first electrode annulus. A second electrode is radially inward of the capacitor insulator. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor- electrode structure. A sense line is electrically coupled to another source/drain region of multiple of the transistors that are in different memory-cell tiers. Additional embodiments and aspects are disclosed, including methods.
(FR) L’invention concerne une barrette de mémoire qui comprend des étages alternés verticalement de matériau isolant et de cellules de mémoire. Les cellules de mémoire comprennent individuellement un transistor et un condensateur. Le condensateur comprend une première électrode couplée électriquement à une zone de source/drain du transistor. La première électrode comprend un anneau dans une section transversale horizontale en ligne droite et un isolant de condensateur radialement vers l’intérieur de l’anneau de la première électrode. Une deuxième électrode se trouve radialement vers l’intérieur de l’isolant de condensateur. Une structure condensateur-électrode s’étend en hauteur à travers les étages alternés verticalement. Des électrodes individuelles parmi les deuxièmes électrodes de condensateurs individuels parmi les condensateurs sont couplées électriquement à la structure condensateur-électrode s’étendant en hauteur. Une ligne de détection est couplée électriquement à une autre zone de source/drain de plusieurs des transistors qui sont dans différents étages de cellules de mémoire. L’invention concerne également des modes de réalisation et des aspects additionnels, dont des procédés.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)