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1. (WO2019050735) METHODS OF PRODUCING SELF-ALIGNED VIAS
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Pub. No.: WO/2019/050735 International Application No.: PCT/US2018/048503
Publication Date: 14.03.2019 International Filing Date: 29.08.2018
IPC:
H01L 21/768 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
Applicants:
MICROMATERIALS LLC [US/US]; 2711 Centerville Road, Suite 400 Wilmington, Delaware 19808, US
Inventors:
ZHANG, Ying; US
FREED, Regina; US
INGLE, Nitin, K.; US
HWANG, Ho-yung; US
MITRA, Uday; US
Agent:
BLANKMAN, Jeffrey, I.; US
Priority Data:
62/555,04106.09.2017US
Title (EN) METHODS OF PRODUCING SELF-ALIGNED VIAS
(FR) PROCÉDÉS DE PRODUCTION DE TROUS D'INTERCONNEXION AUTO-ALIGNÉS
Abstract:
(EN) Methods and apparatus to form fully self-aligned vias are described. A seed gapfill layer is formed on a recessed first insulating layers positioned between first conductive lines. Pillars are formed from the seed gapfill layer and a second insulating layer is deposited in the gaps between pillars. The pillars are removed and a third insulating layer is deposited in the gaps in the second insulating layer to form an overburden of third insulating layer. A portion of the overburden of the third insulating layer is removed to expose the first conductive lines and form vias.
(FR) L'invention concerne des procédés et un appareil pour former des trous d'interconnexion entièrement auto-alignés. Une couche de remplissage de vides en germe est formée sur une première couche isolante évidée positionnée entre des premières lignes conductrices. Des piliers sont formés à partir de la couche de remplissage de vides en germe et une seconde couche isolante est déposée dans les espaces entre les piliers. Les piliers sont retirés et une troisième couche isolante est déposée dans les espaces dans la seconde couche isolante pour former une surcharge de troisième couche isolante. Une partie de la surcharge de la troisième couche isolante est retirée pour exposer les premières lignes conductrices et former des trous d'interconnexion.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)