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1. (WO2019050657) CONFIGURABLE POWER COMBINER AND SPLITTER
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Pub. No.: WO/2019/050657 International Application No.: PCT/US2018/046282
Publication Date: 14.03.2019 International Filing Date: 10.08.2018
IPC:
H03H 7/48 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
H
IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
7
Multiple-port networks comprising only passive electrical elements as network components
48
Networks for connecting several sources or loads, working on the same frequency or frequency band, to a common load or source
Applicants:
QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors:
KU, Bon-Hyun; US
DUNWORTH, Jeremy; US
Agent:
LENKIN, Alan M.; US
LUTZ, Joseph; US
PARTOW-NAVID, Puya; US
FASHU-KANU, Alvin V.; US
Priority Data:
15/940,88829.03.2018US
62/557,08911.09.2017US
Title (EN) CONFIGURABLE POWER COMBINER AND SPLITTER
(FR) COMBINEUR ET DIVISEUR DE PUISSANCE CONFIGURABLES
Abstract:
(EN) A signal processing circuit reduces die size and power consumption for each antenna element. The signal processing circuit (300) includes a first set of ports (PI, P2), a third port (P3), a first path (302), a second path (304) and a first transistor (Tl). The first path (302) is between a first port (PI) of the first set of ports and the third port (P3). The second path (304) is between a second port (P2) of the first set of ports and the third port (P3). The first transistor (Tl) is coupled between the first path (302) and the second path (304). The first transistor (Tl) is configured to receive a control signal (SI) to control the first transistor (Tl) to adjust an impedance between the first path (302) and the second path (304).
(FR) La présente invention concerne un circuit de traitement de signal qui réduit la taille de la puce et la consommation d'énergie pour chaque élément d'antenne. Le circuit de traitement de signal (300) comprend un premier ensemble de ports (PI, P2), un troisième port (P3), un premier trajet (302), un second trajet (304) et un premier transistor (Tl). Le premier trajet (302) se trouve entre un premier port (PI) du premier ensemble de ports et le troisième port (P3). Le second trajet (304) se trouve entre un deuxième port (P2) du premier ensemble de ports et le troisième port (P3). Le premier transistor (Tl) est couplé entre le premier trajet (302) et le second trajet (304). Le premier transistor (Tl) est configuré pour recevoir un signal de commande (SI) permettant de commander le premier transistor (Tl) pour régler une impédance entre le premier trajet (302) et le second trajet (304).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)