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1. (WO2019050579) RESISTIVE RANDOM ACCESS MEMORY DEVICE CONTAINING REPLACEMENT WORD LINES AND METHOD OF MAKING THEREOF
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Pub. No.: WO/2019/050579 International Application No.: PCT/US2018/034697
Publication Date: 14.03.2019 International Filing Date: 25.05.2018
IPC:
H01L 45/00 (2006.01) ,H01L 27/24 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
45
Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
24
including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
Applicants:
SANDISK TECHNOLOGIES LLC [US/US]; 5080 Spectrum Drive Suite 1050W Addison, Texas 75001, US
Inventors:
KIKUCHI, Shin; US
TAKAKI, Seje; US
Agent:
RADOMSKY, Leon; US
COHN, Joanna; US
CONNOR, David; US
GAYOSO, Tony; US
GEMMELL, Elizabeth; US
GILL, Matthew; US
GREGORY, Shaun; US
GUNNELS, Zarema; US
HANSEN, Robert; US
HUANG, Stephen; US
HYAMS, David; US
JOHNSON, Timothy; US
MAZAHERY, Benjamin; US
MURPHY, Timothy; US
NGUYEN, Jacqueline; US
O'BRIEN, Michelle; US
PARK, Byeongju; US
RUTT, Steven; US
SIMON, Phyllis; US
SMITH, Jackson R.; US
SULSKY, Martin; US
Priority Data:
15/695,22505.09.2017US
Title (EN) RESISTIVE RANDOM ACCESS MEMORY DEVICE CONTAINING REPLACEMENT WORD LINES AND METHOD OF MAKING THEREOF
(FR) DISPOSITIF DE MÉMOIRE VIVE RÉSISTIVE CONTENANT DES LIGNES DE MOTS DE REMPLACEMENT ET SON PROCÉDÉ DE FABRICATION
Abstract:
(EN) A method of forming a resistive memory device includes forming an alternating stack of insulating layers and sacrificial material layers that extend along a first horizontal direction over a substrate, forming a laterally alternating sequence of vertical conductive lines and dielectric pillar structures that alternate along the first horizontal direction on sidewalls of the alternating stack, forming lateral recesses by removing the sacrificial material layers selective to the insulating layers, selectively growing resistive memory material portions from physically exposed surfaces of the vertical conductive lines in the lateral recesses, and forming electrically conductive layers over the resistive memory material portions in the lateral recesses.
(FR) Cette invention concerne un procédé de formation d'un dispositif de mémoire résistive, consistant à former un empilement alterné de couches isolantes et de couches de matériau sacrificiel qui s'étendent le long d'une première direction horizontale sur un substrat, former une séquence alternée latéralement de lignes conductrices verticales et de structures de piliers diélectriques qui alternent le long de la première direction horizontale sur les parois latérales de l'empilement alterné, former des évidements latéraux par élimination des couches de matériau sacrificiel sélectivement par rapport aux couches isolantes, développer sélectivement des parties de matériau de mémoire résistive à partir de surfaces physiquement exposées des lignes conductrices verticales dans les évidements latéraux, et former des couches électriquement conductrices sur les parties de matériau de mémoire résistive dans les évidements latéraux.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)