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1. (WO2019050477) PHOTONIC INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING THE SAME
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Pub. No.: WO/2019/050477 International Application No.: PCT/SG2018/050445
Publication Date: 14.03.2019 International Filing Date: 03.09.2018
IPC:
G02B 6/42 (2006.01) ,H01L 21/56 (2006.01)
G PHYSICS
02
OPTICS
B
OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS
6
Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
24
Coupling light guides
42
Coupling light guides with opto-electronic elements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56
Encapsulations, e.g. encapsulating layers, coatings
Applicants:
AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH [SG/SG]; 1 Fusionopolis Way, #20-10 Connexis North Tower, Singapore 138632, SG
Inventors:
LIM, Teck Guan; SG
BHATTACHARYA, Surya; SG
Agent:
VIERING, JENTSCHURA & PARTNER LLP; P.O. Box 1088 Rochor Post Office Rochor Road Singapore 911833, SG
Priority Data:
10201707236R06.09.2017SG
Title (EN) PHOTONIC INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING THE SAME
(FR) BOÎTIER DE CIRCUIT INTÉGRÉ PHOTONIQUE ET SON PROCÉDÉ DE FORMATION
Abstract:
(EN) Various embodiments may relate to a method of forming a photonic integrated circuit package (PIC). The method may include forming a redistribution layer (RDL) over a carrier. The method may also include forming a through hole or cavity on the redistribution layer. The method may additionally include providing a stop-ring structure, the stop-ring structure including a ring of suitable material, the stop-ring structure defining a hollow space, over the redistribution layer so that the hollow space is over the through hole or cavity. The method may further include arranging a photonic integrated circuit (PIC) die over the redistribution layer so that the photonic integrated circuit (PIC) die is on the stop-ring structure. The method may also include forming a molded package by forming a mold structure to at least partially cover the photonic integrated circuit (PIC) die to form the photonic integrated circuit package.
(FR) Divers modes de réalisation peuvent concerner un procédé de formation d'un boîtier de circuit intégré photonique (PIC). Le procédé peut comprendre la formation d'une couche de redistribution (RDL) sur un support. Le procédé peut également comprendre la formation d'un trou traversant ou d'une cavité sur la couche de redistribution. Le procédé peut en outre comprendre la fourniture d'une structure d'anneau d'arrêt, la structure d'anneau d'arrêt comprenant un anneau constitué d'un matériau approprié, la structure d'anneau d'arrêt définissant un espace creux, sur la couche de redistribution de sorte que l'espace creux se trouve au-dessus du trou traversant ou de la cavité. Le procédé peut en outre comprendre l'agencement d'une puce de circuit intégré photonique (PIC) sur la couche de redistribution de telle sorte que la puce de circuit intégré photonique (PIC) se trouve sur la structure d'anneau d'arrêt. Le procédé peut également comprendre la formation d'un boîtier moulé par formation d'une structure de moule pour recouvrir au moins partiellement la puce de circuit intégré photonique (PIC) pour former le boîtier de circuit intégré photonique.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)