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1. (WO2019050266) THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREFOR
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Pub. No.: WO/2019/050266 International Application No.: PCT/KR2018/010352
Publication Date: 14.03.2019 International Filing Date: 05.09.2018
IPC:
H01L 29/786 (2006.01) ,H01L 27/32 (2006.01) ,H01L 21/02 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
28
including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
32
with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
Applicants:
고려대학교 세종산학협력단 KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION, SEJONG CAMPUS [KR/KR]; 세종시 조치원읍 세종로 2511 2511, Sejong-si Jochiwon-eup Sejong 30019, KR
Inventors:
김보성 KIM, Bo Sung; KR
홍문표 HONG, Mun Pyo; KR
김상일 KIM, Sang Il; KR
정현재 JUNG, Hyen Jae; KR
Agent:
박상열 PARK, Sang Youl; KR
Priority Data:
10-2017-011345505.09.2017KR
Title (EN) THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREFOR
(FR) TRANSISTOR À COUCHES MINCES ET SON PROCÉDÉ DE FABRICATION
(KO) 박막 트랜지스터 및 그 제조 방법
Abstract:
(EN) A thin film transistor and a manufacturing method therefor are provided. The manufacturing method for a thin film transistor comprises the steps of: preparing a substrate; forming a first semiconductor layer on the substrate; forming a second semiconductor layer thinner than the first semiconductor layer on the first semiconductor layer; patterning the first semiconductor layer and the second semiconductor layer; forming a gate insulating film on the second semiconductor layer; and forming a gate electrode on the gate insulating film, wherein the first semiconductor layer is formed by DC sputtering under an oxygen atmosphere, and the second semiconductor layer is formed at a lower rate than the first semiconductor layer under an oxygen-deficient condition.
(FR) L'invention concerne un transistor à couches minces et son procédé de fabrication. Le procédé de fabrication du transistor à couches minces comprend les étapes suivantes : préparation d'un substrat; formation d'une première couche semi-conductrice sur le substrat; formation d'une seconde couche semi-conductrice plus mince que la première couche semi-conductrice sur la première couche semi-conductrice; formation de motifs sur la première couche semi-conductrice et la seconde couche semi-conductrice; formation d'un film d'isolation de grille sur la seconde couche semi-conductrice; et formation d'une électrode de grille sur le film d'isolation de grille, la première couche semi-conductrice étant formée par pulvérisation cathodique en courant continu sous atmosphère d'oxygène, et la seconde couche semi-conductrice étant formée à une plus faible vitesse que la première couche semi-conductrice dans des conditions d'insuffisance d'oxygène.
(KO) 박막 트랜지스터 및 그 제조 방법이 제공된다. 박막 트랜지스터의 제조 방법은 기판이 준비되는 단계, 상기 기판 상에 제1 반도체 층을 형성하는 단계, 상기 제1 반도체 층 상에, 상기 제1 반도체 층 보다 두께가 얇은 제2 반도체 층을 형성하는 단계, 상기 제1 반도체 층 및 상기 제2 반도체 층을 패터닝하는 단계, 상기 제2 반도체 층 상에 게이트 절연막을 형성하는 단계 및 상기 게이트 절연막 상에 게이트 전극을 형성하는 단계를 포함하되, 상기 제1 반도체 층은 산소 분위기에서DC 스퍼터링(sputtering)으로 형성되고, 상기 제2 반도체 층은 산소 결핍 조건에서 상기 제1 반도체 층보다 느린 속도로 형성된다.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Korean (KO)
Filing Language: Korean (KO)