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1. (WO2019050255) PRINTED CIRCUIT BOARD ASSEMBLY
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Pub. No.: WO/2019/050255 International Application No.: PCT/KR2018/010300
Publication Date: 14.03.2019 International Filing Date: 04.09.2018
IPC:
H05K 1/14 (2006.01) ,H05K 1/02 (2006.01) ,H05K 1/11 (2006.01) ,H05K 1/18 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
14
Structural association of two or more printed circuits
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
11
Printed elements for providing electric connections to or between printed circuits
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
18
Printed circuits structurally associated with non-printed electric components
Applicants:
삼성전자주식회사 SAMSUNG ELECTRONICS CO., LTD. [KR/KR]; 경기도 수원시 영통구 삼성로 129 129, Samsung-ro Yeongtong-gu Suwon-si Gyeonggi-do 16677, KR
Inventors:
황보훈 HWANG, Bo Hoon; KR
Agent:
특허법인 세림 SELIM INTELLECTUAL PROPERTY LAW FIRM; 서울시 서초구 강남대로 285 태우빌딩 10층,11층 10F and 11F, Taewoo Bldg. 285, Gangnam-daero Seocho-gu Seoul 06729, KR
Priority Data:
10-2017-011382706.09.2017KR
Title (EN) PRINTED CIRCUIT BOARD ASSEMBLY
(FR) ENSEMBLE CARTE DE CIRCUIT IMPRIMÉ
(KO) 인쇄 회로 기판 어셈블리
Abstract:
(EN) A printed circuit board assembly may comprise: a main printed circuit board; and a sub printed circuit board mounted on the main printed circuit board. The main printed circuit board may comprise: a first main conductor layer including a first main signal line and a second main signal line; a second main conductor layer including a third main signal line disposed between the first main signal line and the second main signal line; and a main dielectric layer for insulating the first main conductor layer from the second main conductor layer. The sub printed circuit board may comprise: a first sub conductor layer including a first sub signal line connected to the first main signal line and the second main signal line; and a sub dielectric layer for insulating the first sub conductor layer from the first main conductor layer.
(FR) La présente invention concerne un ensemble carte de circuit imprimé qui peut comprendre : une carte de circuit imprimé principale ; et une carte de circuit imprimé secondaire montée sur la carte de circuit imprimé principale. La carte de circuit imprimé principale peut comprendre : une première couche conductrice principale comprenant une première ligne de signal principale et une deuxième ligne de signal principale : une seconde couche conductrice principale comprenant une troisième ligne de signal principale disposée entre la première ligne de signal principale et la deuxième ligne de signal principale ; et une couche diélectrique principale permettant d'isoler la première couche conductrice principale de la deuxième couche conductrice principale. La carte de circuit imprimé secondaire peut comprendre : une première sous-couche de sous-conducteur comprenant une première sous-ligne de signal connectée à la première ligne de signal principale et à la deuxième ligne de signal principale ; et une sous-couche diélectrique permettant d'isoler la première sous-couche conductrice de la première couche conductrice principale.
(KO) 인쇄 회로 기판 어셈블리는, 메인 인쇄 회로 기판과, 메인 인쇄 회로 기판 상에 실장되는 서브 인쇄 회로 기판을 포함할 수 있다. 메인 인쇄 회로 기판은, 제1 메인 신호 라인과 제2 메인 신호 라인을 포함하는 제1 메인 전도체 층; 제1 메인 신호 라인과 제2 메인 신호 라인 사이에 배치된 제3 메인 신호 라인을 포함하는 제2 메인 전도체 층; 및 제1 메인 전도체 층과 제2 메인 전도체 층을 절연하는 메인 유전체 층을 포함할 수 있다. 서브 인쇄 회로 기판은, 제1 메인 신호 라인과 제2 메인 신호 라인과 연결된 제1 서브 신호 라인을 포함하는 제1 서브 전도체 층; 및 제1 서브 전도체 층과 제1 메인 전도체 층을 절연하는 서브 유전체 층을 포함할 수 있다.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Korean (KO)
Filing Language: Korean (KO)