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1. (WO2019049980) RECONFIGURATION CIRCUIT
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/049980 International Application No.: PCT/JP2018/033178
Publication Date: 14.03.2019 International Filing Date: 07.09.2018
IPC:
H03K 19/177 (2006.01) ,G06F 11/16 (2006.01) ,G11C 29/00 (2006.01) ,H01L 21/8239 (2006.01) ,H01L 27/105 (2006.01) ,H01L 45/00 (2006.01) ,H01L 49/00 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
19
Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02
using specified components
173
using elementary logic circuits as components
177
arranged in matrix form
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
11
Error detection; Error correction; Monitoring
07
Responding to the occurrence of a fault, e.g. fault tolerance
16
Error detection or correction of the data by redundancy in hardware
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
29
Checking stores for correct operation; Testing stores during standby or offline operation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
45
Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
49
Solid state devices not provided for in groups H01L27/-H01L47/99; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
Applicants:
日本電気株式会社 NEC CORPORATION [JP/JP]; 東京都港区芝五丁目7番1号 7-1, Shiba 5-chome, Minato-ku, Tokyo 1088001, JP
Inventors:
辻 幸秀 TSUJI Yukihide; JP
阪本 利司 SAKAMOTO Toshitsugu; JP
宮村 信 MIYAMURA Makoto; JP
根橋 竜介 NEBASHI Ryusuke; JP
多田 あゆ香 TADA Ayuka; JP
白 旭 BAI Xu; JP
Agent:
下坂 直樹 SHIMOSAKA Naoki; JP
Priority Data:
2017-17418211.09.2017JP
Title (EN) RECONFIGURATION CIRCUIT
(FR) CIRCUIT DE RECONFIGURATION
(JA) 再構成回路
Abstract:
(EN) In order to achieve both high-density implementation of applications in the form a reconfiguration circuit without a redundancy bit and the capability to continuously run applications with redundancy, the present invention is a reconfiguration circuit provided with: a first lookup table composed of a crossbar memory formed in a crossbar switching circuit having a plurality of switch cells including a complementary element and a multiplexer for selecting and outputting at least one of a plurality of signals input from the crossbar memory; a second lookup table composed of a crossbar memory and a multiplexer; and a switch that is connected to an output node of the first lookup table and to an output node of the second lookup table and that switches the output node of the first lookup table and the output node of the second lookup table to an electrically conductive state or a non-conductive state.
(FR) La présente invention a pour objet d'atteindre une mise en œuvre à haute densité d'applications sous la forme d'un circuit de reconfiguration sans bit de redondance ainsi que la capacité d'exécuter en continu des applications avec redondance. Plus particulièrement, l'invention concerne un circuit de reconfiguration comprenant : une première table de consultation composée d'une mémoire à barres croisées formée dans un circuit de commutation à barres croisées ayant une pluralité de cellules de commutation comprenant un élément complémentaire et un multiplexeur pour sélectionner et délivrer en sortie au moins l'un d'une pluralité de signaux entrés à partir de la mémoire à barres croisées ; une seconde table de consultation composée d'une mémoire à barres croisées et d'un multiplexeur ; et un commutateur qui est connecté à un nœud de sortie de la première table de consultation et à un nœud de sortie de la seconde table de consultation et qui commute le nœud de sortie de la première table de consultation et le nœud de sortie de la seconde table de consultation vers un état conducteur ou un état non conducteur.
(JA) 冗長ビットを持たない再構成回路としてアプリケーションを高密度に実装することと、冗長性を持たせて継続的なアプリケーション動作を可能とすることを両立するために、相補型素子を含む複数のスイッチセルを有するクロスバースイッチ回路に構成されるクロスバーメモリと、クロスバーメモリから入力される複数の信号のうち少なくとも一つを選択して出力するマルチプレクサとによって構成される第1のルックアップテーブルと、クロスバーメモリとマルチプレクサとによって構成される第2のルックアップテーブルと、第1のルックアップテーブルの出力ノードと、第2のルックアップテーブルの出力ノードとに接続され、第1のルックアップテーブルの出力ノードと第2のルックアップテーブルの出力ノードとを電気的に導通もしくは非導通の状態に切り替えるスイッチとを備える再構成回路とする。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)