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1. (WO2019049900) SEMICONDUCTOR WAFER MANUFACTURING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR ENERGY BEAM DETECTING ELEMENT, AND SEMICONDUCTOR WAFER
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Pub. No.: WO/2019/049900 International Application No.: PCT/JP2018/032912
Publication Date: 14.03.2019 International Filing Date: 05.09.2018
IPC:
H01L 31/10 (2006.01) ,H01L 31/08 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
31
Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength, or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
08
in which radiation controls flow of current through the device, e.g. photoresistors
10
characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
31
Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength, or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
08
in which radiation controls flow of current through the device, e.g. photoresistors
Applicants:
浜松ホトニクス株式会社 HAMAMATSU PHOTONICS K.K. [JP/JP]; 静岡県浜松市東区市野町1126番地の1 1126-1, Ichino-cho, Higashi-ku, Hamamatsu-shi, Shizuoka 4358558, JP
Inventors:
小杉 和正 KOSUGI Kazumasa; JP
鎌田 真太郎 KAMADA Shintaro; JP
山村 和久 YAMAMURA Kazuhisa; JP
Agent:
長谷川 芳樹 HASEGAWA Yoshiki; JP
黒木 義樹 KUROKI Yoshiki; JP
柴山 健一 SHIBAYAMA Kenichi; JP
Priority Data:
2017-17304908.09.2017JP
Title (EN) SEMICONDUCTOR WAFER MANUFACTURING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR ENERGY BEAM DETECTING ELEMENT, AND SEMICONDUCTOR WAFER
(FR) PROCÉDÉ DE FABRICATION DE TRANCHE SEMI-CONDUCTRICE, PROCÉDÉ DE FABRICATION D'ÉLÉMENT DE DÉTECTION DE FAISCEAU D'ÉNERGIE DE SEMI-CONDUCTEUR, ET TRANCHE SEMI-CONDUCTRICE
(JA) 半導体ウエハの製造方法、半導体エネルギー線検出素子の製造方法、及び半導体ウエハ
Abstract:
(EN) A through-slit is provided in a semiconductor wafer. A first virtual cutting line defines, as viewed from a direction orthogonal to a first major surface, a chip portion including an energy beam sensitive region. A second virtual cutting line has a smaller minimum distance to the edge of a second semiconductor region compared to the first virtual cutting line. The through-slit penetrates through the semiconductor wafer along the second virtual cutting line in a thickness direction. Providing the through-slit results in the formation of a side surface in the chip portion exposing a first semiconductor region 3. Impurities are added to the side surface exposing the first semiconductor region 3, whereby a fourth semiconductor region of a first conductivity type is provided on the side surface side of the chip portion.
(FR) L'invention concerne une fente traversante disposée dans une tranche semi-conductrice. Une première ligne de découpe virtuelle définit, vue depuis une direction orthogonale à une première surface principale, une partie de puce comprenant une région sensible à un faisceau d'énergie. Une seconde ligne de découpe virtuelle a une distance minimale inférieure au bord d'une seconde région semi-conductrice par rapport à la première ligne de découpe virtuelle. La fente traversante pénètre à travers la tranche semi-conductrice le long de la seconde ligne de découpe virtuelle dans une direction d'épaisseur. La fourniture de la fente traversante permet la formation d'une surface latérale dans la partie de puce exposant une première région semi-conductrice 3. Des impuretés sont ajoutées à la surface latérale exposant la première région semi-conductrice 3, une quatrième région semi-conductrice d'un premier type de conductivité étant disposée sur le côté de surface latérale de la partie de puce.
(JA) 貫通スリットが、半導体ウエハに設けられる。第1仮想切断線は、第1主面に直交する方向から見て、エネルギー線感応領域を含むチップ部を画成している。第2仮想切断線は、第1仮想切断線と該第1仮想切断線よりも第2半導体領域の縁までの最短距離が小さい。貫通スリットは、第2仮想切断線に沿って半導体ウエハを厚さ方向に貫通する。貫通スリットを設けることで、第1半導体領域3が露出する側面がチップ部に形成される。第1半導体領域3が露出する側面への不純物の添加により、第1導電型の第4半導体領域が、チップ部の当該側面側に設けられる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)