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1. (WO2019049718) AVALANCHE PHOTODIODE AND METHOD FOR PREPARING SAME
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Pub. No.: WO/2019/049718 International Application No.: PCT/JP2018/031674
Publication Date: 14.03.2019 International Filing Date: 28.08.2018
IPC:
H01L 31/107 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
31
Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength, or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
08
in which radiation controls flow of current through the device, e.g. photoresistors
10
characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
101
Devices sensitive to infra-red, visible or ultra-violet radiation
102
characterised by only one potential barrier or surface barrier
107
the potential barrier working in avalanche mode, e.g. avalanche photodiode
Applicants:
日本電信電話株式会社 NIPPON TELEGRAPH AND TELEPHONE CORPORATION [JP/JP]; 東京都千代田区大手町一丁目5番1号 5-1, Otemachi 1-chome, Chiyoda-ku, Tokyo 1008116, JP
Inventors:
名田 允洋 NADA, Masahiro; JP
松崎 秀昭 MATSUZAKI, Hideaki; JP
Agent:
山川 茂樹 YAMAKAWA, Shigeki; JP
小池 勇三 KOIKE, Yuzo; JP
山川 政樹 YAMAKAWA, Masaki; JP
Priority Data:
2017-17098806.09.2017JP
Title (EN) AVALANCHE PHOTODIODE AND METHOD FOR PREPARING SAME
(FR) PHOTODIODE À AVALANCHE ET SON PROCÉDÉ DE PRÉPARATION
(JA) アバランシェフォトダイオードおよびその製造方法
Abstract:
(EN) According to the present invention, an n-type semiconductor layer (102), a multiplication layer (103), an electric field control layer (104), a light absorption layer (105) and a p-type semiconductor layer (106) are formed on a growth substrate (101), and then the p-type semiconductor layer (106) is attached to a transfer substrate (107). Thereafter, the growth substrate (101) is removed, and the n-type semiconductor layer (102) is processed to have an area smaller than the multiplication layer (103).
(FR) Selon la présente invention, une couche semi-conductrice de type n (102), une couche de multiplication (103), une couche de commande de champ électrique (104), une couche d'absorption de lumière (105) et une couche semi-conductrice de type p (106) sont formées sur un substrat de croissance (101), puis la couche semi-conductrice de type p (106) est fixée à un substrat de transfert (107). Ensuite, le substrat de croissance (101) est retiré, et la couche semi-conductrice de type n (102) est traitée pour avoir une zone plus petite que la couche de multiplication (103).
(JA) n型半導体層(102)、増倍層(103)、電界制御層(104)、光吸収層(105)、p型半導体層(106)を成長基板(101)の上に形成した後で、p型半導体層(106)を転写基板(107)に貼り付ける。この後、成長基板(101)を除去し、n型半導体層(102)を、増倍層(103)より小さい面積に加工する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)