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1. (WO2019049654) NEURAL NETWORK COMPUTATION CIRCUIT USING SEMICONDUCTOR STORAGE ELEMENT
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Pub. No.: WO/2019/049654 International Application No.: PCT/JP2018/030862
Publication Date: 14.03.2019 International Filing Date: 21.08.2018
IPC:
G06N 3/063 (2006.01) ,G06G 7/60 (2006.01) ,G11C 11/54 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
N
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3
Computer systems based on biological models
02
using neural network models
06
Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
063
using electronic means
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
G
ANALOGUE COMPUTERS
7
Devices in which the computing operation is performed by varying electric or magnetic quantities
48
Analogue computers for specific processes, systems, or devices, e.g. simulators
60
for living beings, e.g. their nervous systems
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
54
using elements simulating biological cells, e.g. neuron
Applicants:
パナソニック株式会社 PANASONIC CORPORATION [JP/JP]; 大阪府門真市大字門真1006番地 1006, Oaza Kadoma, Kadoma-shi, Osaka 5718501, JP
Inventors:
中山 雅義 NAKAYAMA, Masayoshi; --
河野 和幸 KOUNO, Kazuyuki; --
早田 百合子 HAYATA, Yuriko; --
小野 貴史 ONO, Takashi; --
持田 礼司 MOCHIDA, Reiji; --
Agent:
新居 広守 NII, Hiromori; JP
寺谷 英作 TERATANI, Eisaku; JP
道坂 伸一 MICHISAKA, Shinichi; JP
Priority Data:
2017-17209407.09.2017JP
Title (EN) NEURAL NETWORK COMPUTATION CIRCUIT USING SEMICONDUCTOR STORAGE ELEMENT
(FR) CIRCUIT DE CALCUL DE RÉSEAU NEURONAL UTILISANT UN ÉLÉMENT DE STOCKAGE À SEMI-CONDUCTEUR
(JA) 半導体記憶素子を用いたニューラルネットワーク演算回路
Abstract:
(EN) A neural network computation circuit comprising an in-area word line multiple selection circuit for logically segmenting a plurality of word lines of a memory array (10) into a plurality of word line areas and making a given word line selected or unselected for each of the word line areas. The in-area word line multiple selection circuit comprises a first latch (31) and a second latch (32) for each of the word lines.
(FR) L'invention concerne un circuit de calcul de réseau neuronal qui comprend un circuit de sélection de multiples lignes de mots en zone pour segmenter de manière logique une pluralité de lignes de mots d'un réseau de mémoire (10) en une pluralité de zones de ligne de mots et pour rendre une ligne de mots donnée sélectionnée ou non sélectionnée pour chacune des zones de ligne de mots. Le circuit de sélection de multiples lignes de mots en zone comprend un premier verrou (31) et un second verrou (32) pour chacune des lignes de mots.
(JA) メモリアレイ(10)の複数のワード線を論理的に複数のワード線エリアに分割し、ワード線エリアごとに、任意のワード線を選択あるいは非選択にするエリア内ワード線多重選択回路を備え、エリア内ワード線多重選択回路は第一のラッチ(31)および第二のラッチ(32)をワード線毎に備える。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)