Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2019049572) SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR DEVICE PRODUCTION METHOD
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/049572 International Application No.: PCT/JP2018/029195
Publication Date: 14.03.2019 International Filing Date: 03.08.2018
IPC:
H01L 29/78 (2006.01) ,H01L 21/3205 (2006.01) ,H01L 21/60 (2006.01) ,H01L 21/768 (2006.01) ,H01L 23/522 (2006.01) ,H01L 29/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
Applicants:
富士電機株式会社 FUJI ELECTRIC CO., LTD. [JP/JP]; 神奈川県川崎市川崎区田辺新田1番1号 1-1, Tanabeshinden, Kawasaki-ku, Kawasaki-shi, Kanagawa 2109530, JP
Inventors:
熊田 恵志郎 KUMADA, Keishirou; JP
橋爪 悠一 HASHIZUME, Yuichi; JP
星 保幸 HOSHI, Yasuyuki; JP
鈴木 啓久 SUZUKI, Yoshihisa; JP
Agent:
酒井 昭徳 SAKAI, Akinori; JP
Priority Data:
2017-17068005.09.2017JP
Title (EN) SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR DEVICE PRODUCTION METHOD
(FR) DISPOSITIF À SEMI-CONDUCTEUR AU CARBURE DE SILICIUM ET PROCÉDÉ DE PRODUCTION DE DISPOSITIF À SEMI-CONDUCTEUR AU CARBURE DE SILICIUM
(JA) 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
Abstract:
(EN) This silicon carbide semiconductor device comprises: a first electroconductive type first semiconductor layer (2) provided on the outer surface of a first electroconductive type semiconductor substrate (1); a second electroconductive type second semiconductor layer (3); a first electroconductive type first semiconductor region (7); and striped gate electrodes (10) provided through a gate insulation film (9). In addition, this silicon carbide semiconductor device comprises a first electrode (13) provided on the surfaces of the second semiconductor layer (3) and the first semiconductor region (7), a plating film (16) selectively provided above the first electrode (13), and solder (17) that anchors a pin-shaped electrode (19) for extracting an external signal to the plating film (16). In a region facing the first electrode (13) where the solder (17) and the plating film (16) are provided, the gate electrodes (10) have a protruding portion extending in a direction that intersects the stripes, and the gate electrodes (10) are connected to one another.
(FR) L'invention concerne un dispositif à semi-conducteur au carbure de silicium comprenant : une première couche semi-conductrice de premier type d'électroconductivité (2) disposée sur la surface externe d'un premier substrat semi-conducteur de premier type d'électroconductivité (1) ; une seconde couche semi-conductrice de second type d'électroconductivité (3) ; une première région semi-conductrice de premier type d'électroconductivité (7) ; et des électrodes de grille en bandes (10) disposées à travers un film d'isolation de grille (9). De plus, ce dispositif à semi-conducteur au carbure de silicium comprend une première électrode (13) disposée sur les surfaces de la seconde couche semi-conductrice (3) et de la première région semi-conductrice (7), un film de placage (16) disposé sélectivement au-dessus de la première électrode (13), et une brasure (17) qui ancre une électrode en forme de broche (19) pour extraire un signal externe vers le film de placage (16). Dans une région faisant face à la première électrode (13) où la brasure (17) et le film de placage (16) sont prévus, les électrodes de grille (10) ont une partie en saillie s'étendant dans une direction qui coupe les bandes, et les électrodes de grille (10) sont reliées les unes aux autres.
(JA) 炭化珪素半導体装置は、第1導電型の半導体基板(1)のおもて面に設けられた第1導電型の第1半導体層(2)と、第2導電型の第2半導体層(3)と、第1導電型の第1半導体領域(7)と、ゲート絶縁膜(9)を介して設けられたストライプ形状のゲート電極(10)と、を備える。また、第2半導体層(3)と第1半導体領域(7)の表面に設けられた第1電極(13)と、第1電極(13)上に、選択的に設けられためっき膜(16)と、めっき膜(16)上に外部信号をとり出すピン状電極(19)を固着するはんだ(17)と、を備える。ゲート電極(10)は、はんだ(17)およびめっき膜(16)が設けられた第1電極(13)と対向する領域において、ストライプ形状と交わる方向に延在した凸部分を有し、ゲート電極(10)同士が接続されている。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)