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1. (WO2019049545) MULTIPLEXER, HIGH FREQUENCY FRONT END CIRCUIT AND COMMUNICATION DEVICE
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Pub. No.: WO/2019/049545 International Application No.: PCT/JP2018/028010
Publication Date: 14.03.2019 International Filing Date: 26.07.2018
IPC:
H03H 7/46 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
H
IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
7
Multiple-port networks comprising only passive electrical elements as network components
46
Networks for connecting several sources or loads, working on different frequencies or frequency bands, to a common load or source
Applicants:
株式会社村田製作所 MURATA MANUFACTURING CO., LTD. [JP/JP]; 京都府長岡京市東神足1丁目10番1号 10-1, Higashikotari 1-chome, Nagaokakyo-shi, Kyoto 6178555, JP
Inventors:
森 弘嗣 MORI, Hirotsugu; JP
Agent:
吉川 修一 YOSHIKAWA, Shuichi; JP
傍島 正朗 SOBAJIMA, Masaaki; JP
Priority Data:
2017-17270008.09.2017JP
Title (EN) MULTIPLEXER, HIGH FREQUENCY FRONT END CIRCUIT AND COMMUNICATION DEVICE
(FR) MULTIPLEXEUR, CIRCUIT FRONTAL À HAUTE FRÉQUENCE ET DISPOSITIF DE COMMUNICATION
(JA) マルチプレクサ、高周波フロントエンド回路及び通信装置
Abstract:
(EN) This multiplexer (1) is provided with: a demultiplexing circuit (11) having a common terminal (110c) and individual terminals (111 and 112), and a filter (21) connected to the individual terminal (111) and a filter (22) connected to the individual terminal (112). The demultiplexing circuit (11) is also provided with: an impedance circuit (Z1) provided in series on a path (r1) connecting the common terminal (110c) and the individual terminal (111); an impedance circuit (Z2) provided in series on a path (r2) connecting the common terminal (110c) and the individual terminal (112); an impedance circuit (Z3); and a switching circuit (12). The switching circuit (12) connects only one of a node (N1) on the path (r1) between the impedance circuit (Z1) and the individual terminal (111) and a node (N2) on the path (r2) between the impedance circuit (Z2) and the individual terminal (112) to the ground through the impedance circuit (Z3).
(FR) Multiplexeur (1) comportant : un circuit de démultiplexage (11) ayant une borne commune (110c) et des bornes individuelles (111 et 112), et un filtre (21) connecté à la borne individuelle (111) et un filtre (22) connecté à la borne individuelle (112). Le circuit de démultiplexage (11) comprend également : un circuit d'impédance (Z1) disposé en série sur un trajet (r1) reliant la borne commune (110c) et la borne individuelle (111) ; un circuit d'impédance (Z2) disposé en série sur un chemin (r2) reliant la borne commune (110c) et la borne individuelle (112) ; un circuit d'impédance (Z3) ; et un circuit de commutation (12). Le circuit de commutation (12) connecte uniquement l'un d'un nœud (N1) sur le trajet (r1) entre le circuit d'impédance (Z1) et la borne individuelle (111) et d'un nœud (N2) sur le trajet (r2) entre le circuit d'impédance (Z2) et la borne individuelle (112) au sol par l'intermédiaire du circuit d'impédance (Z3).
(JA) マルチプレクサ(1)は、共通端子(110c)、個別端子(111及び112)を有する分波回路(11)と、個別端子(111)に接続されたフィルタ(21)と個別端子(112)に接続されたフィルタ(22)とを備える。分波回路(11)は、さらに、共通端子(110c)と個別端子(111)とを接続する経路(r1)上に直列に設けられたインピーダンス回路(Z1)と、共通端子(110c)と個別端子(112)とを接続する経路(r2)上に直列に設けられたインピーダンス回路(Z2)と、インピーダンス回路(Z3)及びスイッチ回路(12)と、を備える。スイッチ回路(12)は、インピーダンス回路(Z1)と個別端子(111)との間の経路(r1)上のノード(N1)、及び、インピーダンス回路(Z2)と個別端子(112)との間の経路(r2)上のノード(N2)のうち一方のみを、インピーダンス回路(Z3)を介してグランドに接続する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)