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1. (WO2019049519) CIRCUIT BOARD AND MANUFACTURING METHOD THEREFOR
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Pub. No.: WO/2019/049519 International Application No.: PCT/JP2018/027095
Publication Date: 14.03.2019 International Filing Date: 19.07.2018
IPC:
H05K 1/03 (2006.01) ,B32B 27/12 (2006.01) ,B32B 27/30 (2006.01) ,H01L 23/12 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
03
Use of materials for the substrate
B PERFORMING OPERATIONS; TRANSPORTING
32
LAYERED PRODUCTS
B
LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
27
Layered products essentially comprising synthetic resin
12
next to a fibrous or filamentary layer
B PERFORMING OPERATIONS; TRANSPORTING
32
LAYERED PRODUCTS
B
LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
27
Layered products essentially comprising synthetic resin
30
comprising vinyl resin; comprising acrylic resin
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
Applicants:
日本ピラー工業株式会社 NIPPON PILLAR PACKING CO., LTD. [JP/JP]; 大阪府大阪市西区新町1丁目7番1号 7-1, Shinmachi 1-chome, Nishi-ku, Osaka-shi, Osaka 5500013, JP
Inventors:
奥長 剛 OKUNAGA, Takeshi; JP
小林 美幸 KOBAYASHI, Miyuki; JP
玉木 達也 TAMAKI, Tatsuya; JP
山崎 健平 YAMASAKI, Kenpei; JP
林 友希 HAYASHI, Tomoki; JP
Agent:
立花 顕治 TACHIBANA, Kenji; JP
Priority Data:
2017-17134806.09.2017JP
Title (EN) CIRCUIT BOARD AND MANUFACTURING METHOD THEREFOR
(FR) CARTE DE CIRCUIT IMPRIMÉ ET SON PROCÉDÉ DE FABRICATION
(JA) 回路基板及びその製造方法
Abstract:
(EN) The circuit board according to the present invention is provided with: a first layer which contains a fiber base material and a meltable fluorine-based resin impregnating the fiber base material; and second layers which are respectively disposed on both surfaces of the first layer and which each contain a non-meltable fluorine-based resin.
(FR) La présente invention concerne une carte de circuit imprimé, comprenant : une première couche qui contient un matériau de base en fibres et une résine à base de fluor fusible imprégnant le matériau de base en fibres ; et de secondes couches qui sont respectivement disposées sur les deux surfaces de la première couche et dont chacune contient une résine à base de fluor non fusible.
(JA) 本発明に係る回路基板は、繊維基材、及び当該繊維機材に含浸される溶融性のフッ素系樹脂を含む第1層と、前記第1層の両面にそれぞれ配置され、非溶融性のフッ素系樹脂を含む、第2層と、を備えている。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)