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1. (WO2019049498) SEMICONDUCTOR INTEGRATED CIRCUIT
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Pub. No.: WO/2019/049498 International Application No.: PCT/JP2018/025628
Publication Date: 14.03.2019 International Filing Date: 06.07.2018
IPC:
H01L 21/82 (2006.01) ,H01L 21/822 (2006.01) ,H01L 27/04 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
Applicants:
ソニーセミコンダクタソリューションズ株式会社 SONY SEMICONDUCTOR SOLUTIONS CORPORATION [JP/JP]; 神奈川県厚木市旭町四丁目14番1号 4-14-1 Asahi-cho, Atsugi-shi, Kanagawa 2430014, JP
Inventors:
田中 義則 TANAKA, Yoshinori; JP
Agent:
丸島 敏一 MARUSHIMA, Toshikazu; JP
Priority Data:
2017-17380811.09.2017JP
Title (EN) SEMICONDUCTOR INTEGRATED CIRCUIT
(FR) CIRCUIT INTÉGRÉ À SEMI-CONDUCTEURS
(JA) 半導体集積回路
Abstract:
(EN) This semiconductor integrated circuit simplifies the wiring shape of a pair of signal wires wired therein. An output circuit outputs a prescribed differential signal from a positive-side output terminal and a negative-side output terminal. A logic circuit is provided with a plurality of positive-side transistors, each gate of which is arrayed in a prescribed direction, and a plurality of negative-side transistors, each gate of which is arrayed in a prescribed direction. A positive-side signal line is wired along the prescribed direction from the positive-side output terminal and connects each of the gates of the plurality of positive-side transistors with the positive-side output terminal. A negative-side signal line is wired along the prescribed direction from the negative-side output terminal and connects each of the gates of the plurality of negative-side transistors with the negative-side output terminal.
(FR) La présente invention concerne un circuit intégré à semi-conducteurs qui simplifie la forme de câblage d'une paire de fils de signal câblés à l'intérieur. Un circuit de sortie émet un signal différentiel prescrit à partir d'une borne de sortie côté positif et d'une borne de sortie côté négatif. Un circuit logique est pourvu d'une pluralité de transistors côté positif, dont chaque grille est disposée en réseau dans une direction prescrite, et d'une pluralité de transistors côté négatif, dont chaque grille est disposée en réseau dans une direction prescrite. Une ligne de signal côté positif est câblée le long de la direction prescrite à partir de la borne de sortie côté positif et connecte chacune des grilles de la pluralité de transistors côté positif à la borne de sortie côté positif. Une ligne de signal côté négatif est câblée le long de la direction prescrite à partir de la borne de sortie côté négatif et connecte chacune des grilles de la pluralité de transistors côté négatif à la borne de sortie côté négatif.
(JA) 一対の信号線が配線される半導体集積回路において、それらの信号線の配線形状を簡素化する。 出力回路は、所定の差動信号を正側出力端子および負側出力端子から出力する。論理回路には、それぞれのゲートが所定方向に配列された複数の正側トランジスタとそれぞれのゲートが所定方向に配列された複数の負側トランジスタとが配置される。正側信号線は、正側出力端子から前記所定方向に沿って配線されて複数の正側トランジスタのそれぞれの前記ゲートと正側出力端子とを接続する。負側信号線は、負側出力端子から前記所定方向に沿って配線されて複数の負側トランジスタのそれぞれのゲートと負側出力端子とを接続する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)