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1. (WO2019049244) TUNNEL MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY
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Pub. No.: WO/2019/049244 International Application No.: PCT/JP2017/032148
Publication Date: 14.03.2019 International Filing Date: 06.09.2017
IPC:
H01L 29/82 (2006.01) ,H01L 21/8239 (2006.01) ,H01L 27/105 (2006.01) ,H01L 43/08 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
82
controllable by variation of the magnetic field applied to the device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
43
Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
08
Magnetic-field-controlled resistors
Applicants:
TDK株式会社 TDK CORPORATION [JP/JP]; 東京都中央区日本橋二丁目5番1号 2-5-1, Nihonbashi, Chuo-ku, Tokyo 1036128, JP
Inventors:
佐々木 智生 SASAKI Tomoyuki; JP
Agent:
長谷川 芳樹 HASEGAWA Yoshiki; JP
黒木 義樹 KUROKI Yoshiki; JP
三上 敬史 MIKAMI Takafumi; JP
Priority Data:
Title (EN) TUNNEL MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY
(FR) ÉLÉMENT À EFFET DE MAGNÉTORÉSISTANCE À EFFET TUNNEL ET MÉMOIRE MAGNÉTIQUE
(JA) トンネル磁気抵抗効果素子及び磁気メモリ
Abstract:
(EN) This TMR element is provided with: a reference layer; a magnetization free layer; a tunnel barrier layer between the reference layer and the magnetization free layer; and a vertical magnetization inducing layer and a leak layer which are stacked on the magnetization free layer on the opposite side from the tunnel barrier layer side. The magnetization direction of the reference layer is fixed in a stacking direction. The vertical magnetization inducing layer provides the magnetization free layer with magnetic anisotropy in a direction aligned with the stacking direction. The leak layer is disposed over an end region in an in-plane direction of the magnetization free layer. The vertical magnetization inducing layer is disposed over at least a central region in the in-plane direction of the magnetization free layer. The leak layer has a smaller resistance value in the stacking direction per in-plane unit area than the vertical magnetization inducing layer.
(FR) La présente invention concerne un élément TMR qui comporte : une couche de référence ; une couche dépourvue de magnétisation ; une couche de barrière à effet tunnel entre la couche de référence et la couche dépourvue de magnétisation ; et une couche d’induction de magnétisation verticale et une couche de fuite qui sont empilées sur la couche dépourvue de magnétisation du côté opposé au côté de la couche de barrière à effet tunnel. La direction de magnétisation de la couche de référence est fixée dans une direction d’empilement. La couche d’induction de magnétisation verticale confère à la couche dépourvue de magnétisation une anisotropie magnétique dans une direction alignée à la direction d’empilement. La couche de fuite est disposée au-dessus d’une zone d’extrémité dans une direction dans le plan de la couche dépourvue de magnétisation. La couche d’induction de magnétisation verticale est disposée au-dessus d’au moins une zone centrale dans la direction dans le plan de la couche dépourvue de magnétisation. La couche de fuite a une valeur de résistance inférieure dans la direction d’empilement par unité d’aire dans le plan à celle de la couche d’induction de magnétisation verticale.
(JA) TMR素子は、参照層と、磁化自由層と、これらの間のトンネルバリア層と、磁化自由層のトンネルバリア層側とは反対側に積層された垂直磁化誘起層及びリーク層とを備える。参照層の磁化方向は、積層方向に沿って固定されており、垂直磁化誘起層は、磁化自由層に積層方向に沿った方向の磁気異方性を付与し、リーク層は、磁化自由層の面内方向の端部領域上に設けられており、垂直磁化誘起層は、磁化自由層の面内方向の少なくとも中央領域上に設けられており、リーク層は、垂直磁化誘起層よりも、面内の単位面積当たりの積層方向に沿った抵抗値が小さい。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)