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1. (WO2019049013) SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/049013 International Application No.: PCT/IB2018/056697
Publication Date: 14.03.2019 International Filing Date: 03.09.2018
IPC:
G11C 5/02 (2006.01) ,G11C 7/12 (2006.01) ,G11C 11/4091 (2006.01) ,H01L 21/8242 (2006.01) ,H01L 27/10 (2006.01) ,H01L 27/108 (2006.01) ,H01L 29/786 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
5
Details of stores covered by group G11C11/63
02
Disposition of storage elements, e.g. in the form of a matrix array
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
7
Arrangements for writing information into, or reading information out from, a digital store
12
Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
34
using semiconductor devices
40
using transistors
401
forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063
Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407
for memory cells of the field-effect type
409
Read-write (R-W) circuits
4091
Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
8242
Dynamic random access memory structures (DRAM)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants:
株式会社半導体エネルギー研究所 SEMICONDUCTOR ENERGY LABORATORY CO., LTD. [JP/JP]; 神奈川県厚木市長谷398 398, Hase, Atsugi-shi, Kanagawa 2430036, JP
Inventors:
大貫達也 ONUKI, Tatsuya; JP
松嵜隆徳 MATSUZAKI, Takanori; JP
加藤清 KATO, Kiyoshi; JP
山崎舜平 YAMAZAKI, Shunpei; JP
Priority Data:
2017-17076606.09.2017JP
2017-17111606.09.2017JP
Title (EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置
Abstract:
(EN) Provided is a novel semiconductor device. The semiconductor device comprises a plurality of cell arrays and a plurality of peripheral circuits, wherein each cell array has a plurality of memory cells; each peripheral circuit has a first drive circuit, a second drive circuit, a first amplification circuit, a second amplification circuit, a third amplification circuit and a fourth amplification circuit; the first drive circuit and the second drive circuit have the function of supplying a selection signal to a cell array; the first amplification circuit and the second amplification circuit have the function of amplifying a potential inputted from a cell array; the third amplification circuit and the fourth amplification circuit have the function of amplifying a potential inputted from the first amplification circuit or the second amplification circuit; the first drive circuit, the second drive circuit, the first amplification circuit, the second amplification circuit, the third amplification circuit and the fourth amplification circuit each have a region overlapping a cell array; and the memory cells include a metal oxide in the channel formation region.
(FR) L’invention concerne un nouveau dispositif à semi-conducteur. Le dispositif à semi-conducteur comprend une pluralité de réseaux de cellules et une pluralité de circuits périphériques, chaque réseau de cellules comportant une pluralité de cellules de mémoire ; chaque circuit périphérique comporte un premier circuit d'attaque, un second circuit d'attaque, un premier circuit d'amplification, un second circuit d'amplification, un troisième circuit d'amplification et un quatrième circuit d'amplification ; le premier circuit d'attaque et le second circuit d'attaque ont pour fonction de fournir un signal de sélection à un réseau de cellules ; le premier circuit d'amplification et le second circuit d'amplification ont pour fonction d'amplifier un potentiel entré à partir d'un réseau de cellules ; le troisième circuit d'amplification et le quatrième circuit d'amplification ont pour fonction d'amplifier un potentiel entré à partir du premier circuit d'amplification ou du second circuit d'amplification ; le premier circuit d'attaque, le second circuit d'attaque, le premier circuit d'amplification, le second circuit d'amplification, le troisième circuit d'amplification et le quatrième circuit d'amplification comportent chacun une région chevauchant un réseau de cellules ; et les cellules de mémoire comprennent un oxyde métallique dans la région de formation de canal.
(JA) 要約書 新規な半導体装置の提供。 複数のセルアレイと、複数の周辺回路と、を有し、セルアレイは、複数のメモリセルを有し、周辺回 路は、第1の駆動回路と、第2の駆動回路と、第1の増幅回路と、第2の増幅回路と、第3の増幅回 路と、 第4の増幅回路と、 を有し、 第1の駆動回路及び第2の駆動回路は、 セルアレイに選択信号を 供給する機能を有し、 第1の増幅回路及び第2の増幅回路は、 セルアレイから入力された電位を増幅 する機能を有し、 第3の増幅回路及び第4の増幅回路は、 第1の増幅回路又は第2の増幅回路から入 力された電位を増幅する機能を有し、 第1の駆動回路と、 第2の駆動回路と、 第1の増幅回路と、 第 2の増幅回路と、 第3の増幅回路と、 第4の増幅回路は、 セルアレイと重なる領域を有し、 メモリセ ルは、チャネル形成領域に金属酸化物を含む半導体装置。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)