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1. (WO2019048828) VOLTAGE REGULATOR
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Pub. No.: WO/2019/048828 International Application No.: PCT/GB2018/052456
Publication Date: 14.03.2019 International Filing Date: 30.08.2018
IPC:
G05F 1/575 (2006.01)
G PHYSICS
05
CONTROLLING; REGULATING
F
SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
1
Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
10
Regulating voltage or current
46
wherein the variable actually regulated by the final control device is dc
56
using semiconductor devices in series with the load as final control devices
575
characterised by the feedback circuit
Applicants:
NORDIC SEMICONDUCTOR ASA [NO/NO]; Otto Nielsens veg 12 7052 Trondheim, NO
SAMUELS, Adrian James [GB/GB]; GB (MG)
Inventors:
FARIAN, Lukasz; NO
Agent:
DEHNS; St Bride's House 10 Salisbury Square London EC4Y 8JD, GB
Priority Data:
1714328.006.09.2017GB
Title (EN) VOLTAGE REGULATOR
(FR) RÉGULATEUR DE TENSION
Abstract:
(EN) A low-dropout voltage regulator (2) is arranged to receive an input voltage (VDD) and produce an output voltage (V0UT)- A pass field-effect-transistor (MPASS) has a first terminal connected to the input voltage and a second terminal arranged to produce the output voltage. An error amplifier (4) is arranged to produce an error signal (VSF) proportional to a difference between a feedback voltage (VFB) and a reference voltage (VREF)- The error signal (VSF) is applied to the gate terminal of a source follower transistor (MNA). The drain terminal of the source follower transistor (MNA) is connected to the input voltage (VDD), and its source terminal is connected to the gate terminal of the pass field-effect-transistor (MPASS)- An adaptive biasing circuit portion (6) is arranged to measure the error signal (VSF) and produce a bias current (lM1, I ADAPTIVE) which depends on said error signal (VSF), and to supply the bias current (lM1, IADAPTIVE) to the source follower transistor (MNA).
(FR) La présente invention concerne un régulateur de tension à faible chute de tension (2) conçu pour recevoir une tension d'entrée (VDD) et produire une tension de sortie (VOUT)-. Un transistor à effet de champ de chute (MPASS) présente une première borne connectée à la tension d'entrée et une seconde borne conçue pour produire la tension de sortie. Un amplificateur d'erreur (4) est conçu pour produire un signal d'erreur (VSF) proportionnel à une différence entre une tension de rétroaction (VFB) et une tension de référence (VREF)-. Le signal d'erreur (VSF) est appliqué à la borne de grille d'un transistor suiveur de source (MNA). La borne de drain du transistor suiveur de source (MNA) est connectée à la tension d'entrée (VDD), et sa borne de source est connectée à la borne de grille du transistor à effet de champ de chute (MPASS)-. Une partie de circuit de polarisation adaptative (6) est conçue pour mesurer le signal d'erreur (VSF) et produire un courant de polarisation (lM1, I ADAPTATIVE) qui dépend dudit signal d'erreur (VSF), et pour fournir le courant de polarisation (lM1, IADAPTATIVE) au transistor suiveur de source (MNA).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)