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1. (WO2019048065) AMPLIFIER CIRCUIT
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Pub. No.: WO/2019/048065 International Application No.: PCT/EP2017/072732
Publication Date: 14.03.2019 International Filing Date: 11.09.2017
IPC:
H03F 3/193 (2006.01) ,H03F 1/32 (2006.01) ,H03F 3/45 (2006.01) ,H03F 3/50 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
3
Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
189
High-frequency amplifiers, e.g. radio frequency amplifiers
19
with semiconductor devices only
193
with field-effect devices
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
1
Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
32
Modifications of amplifiers to reduce non-linear distortion
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
3
Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
45
Differential amplifiers
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
3
Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
50
Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower
Applicants:
TELEFONAKTIEBOLAGET LM ERICSSON (PUBL) [SE/SE]; S-164 83 Stockholm, SE
Inventors:
MASTANTUONO, Daniele; SE
PALM, Mattias; SE
STRANDBERG, Roland; SE
SUNDSTRÖM, Lars; SE
Agent:
ERICSSON; Patent Development Torshamnsgatan 21-23 164 80 STOCKHOLM, SE
Priority Data:
Title (EN) AMPLIFIER CIRCUIT
(FR) CIRCUIT D'AMPLIFICATEUR
Abstract:
(EN) An amplifier circuit (70) that comprises a first and a second field-effect transistor (M1, M2) of the same type is disclosed. It further comprises an input terminal (in) connected to the gate of the second field-effect transistor (M2), an output terminal (out) connected to a node between the drain of the first field-effect transistor (M1) and the source of the second field-effect transistor (M2), and a set of supply terminals configured to receive an upper and a lower supply voltage (VDD, GND), said set comprising a first supply terminal (S1) and a second supply terminal (S2). Moreover, it comprises a first circuit path (P1) connecting the source of the first field-effect transistor (M1) to the first supply terminal (S1), a second circuit path (P2) connecting the drain of the second field-effect transistor (M2) to the second supply terminal, the second circuit path comprising an impedance circuit (Z1), a third circuit path (P3) connecting the gate of the first field-effect transistor (M1) to a circuit node (x) between the impedance circuit (Z1) and the drain of the second field-effect transistor (M2), and a bias circuit (80) configured to generate a bias voltage to the gate of the first field-effect transistor (M1). The bias circuit (80) is controllable to generate the bias voltage as a controllable voltage. The impedance circuit (Z1) is controllable to provide a controllable impedance.
(FR) L'invention concerne un circuit d’amplificateur (70) comprenant un premier et un second transistor à effet de champ (M1, M2) du même type. Il comprend en outre une borne d'entrée (in) connectée à la grille du second transistor à effet de champ (M2), une borne de sortie (out) connectée à un nœud entre le drain du premier transistor à effet de champ (M1) et la source du second transistor à effet de champ (M2), et un ensemble de bornes d'alimentation configurées pour recevoir une tension d'alimentation supérieure et une tension d'alimentation inférieure (VDD, GND), ledit ensemble comprenant une première borne d'alimentation (S1) et une seconde borne d'alimentation (S2). De plus, il comprend un premier chemin de circuit (P1) reliant la source du premier transistor à effet de champ (M1) au premier terminal d'alimentation (S1), un second chemin de circuit (P2) connectant le drain du second transistor à effet de champ (M2) à la seconde borne d'alimentation, le second trajet de circuit comprenant un circuit d'impédance (Z1), un troisième chemin de circuit (P3) connectant la grille du premier transistor à effet de champ (M1) à un nœud de circuit (x) entre le circuit d'impédance (Z1) et le drain du second transistor à effet de champ (M2), et un circuit de polarisation (80) configuré pour générer une tension de polarisation à la grille du premier transistor à effet de champ (M1). Le circuit de polarisation (80) peut être commandé pour générer la tension de polarisation en tant que tension pouvant être commandée. Le circuit d'impédance (Z1) peut être commandé pour fournir une impédance réglable.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)