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1. (WO2019047928) INTERLEAVING METHOD AND INTERLEAVING DEVICE
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Pub. No.: WO/2019/047928 International Application No.: PCT/CN2018/104653
Publication Date: 14.03.2019 International Filing Date: 07.09.2018
IPC:
H04L 1/00 (2006.01)
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
1
Arrangements for detecting or preventing errors in the information received
Applicants:
华为技术有限公司 HUAWEI TECHNOLOGIES CO., LTD. [CN/CN]; 中国广东省深圳市 龙岗区坂田华为总部办公楼 Huawei Administration Building Bantian, Longgang Shenzhen, Guangdong 518129, CN
Inventors:
周悦 ZHOU, Yue; CN
王桂杰 WANG, Guijie; CN
李榕 LI, Rong; CN
杜颖钢 DU, Yinggang; CN
Agent:
北京龙双利达知识产权代理有限公司 LONGSUN LEAD IP LTD.; 中国北京市 海淀区北清路68号院3号楼101 Rm. 101, Building 3 No. 68 Beiqing Road, Haidian District Beijing 100094, CN
Priority Data:
201710806792.508.09.2017CN
Title (EN) INTERLEAVING METHOD AND INTERLEAVING DEVICE
(FR) PROCÉDÉ ET DISPOSITIF D'ENTRELACEMENT
(ZH) 交织方法和交织装置
Abstract:
(EN) An interleaving method capable of improving error correction performance of polar codes is provided. The method comprises: acquiring a first bit sequence, wherein the first bit sequence comprises L bits, and L is a positive integer; writing the L bits into an interleaving matrix according to a preset write rule, wherein the interleaving matrix comprises C columns and R rows, and C and R are positive integers; reading the L bits from the interleaving matrix according to a preset read rule to obtain a second bit sequence, wherein the second bit sequence comprises L bits; and sending the second bit sequence.
(FR) L'invention concerne un procédé d'entrelacement pouvant améliorer les performances de correction d'erreur de codes polaires. Le procédé consiste : à acquérir une première séquence de bits comprenant L bits, L étant un nombre entier positif; à écrire les L bits dans une matrice d'entrelacement selon une règle d'écriture prédéfinie, la matrice d'entrelacement comprenant C colonnes et R rangées, C et R étant des nombres entiers positifs; à lire les L bits à partir de la matrice d'entrelacement, selon une règle de lecture prédéfinie, pour obtenir une seconde séquence de bits comprenant L bits; et à envoyer la seconde séquence de bits.
(ZH) 本申请提供一种交织方法,能够提高极化码的纠错性能。该方法包括:获取第一比特序列,第一比特序列包括L个比特,L为正整数;将所述L个比特按照预设的写入规则写入交织矩阵,交织矩阵包括C行R列,C和R为正整数;按照预设的读取规则从交织矩阵中读取所述L个比特,得到第二比特序列,第二比特序列包括L个比特;发送第二比特序列。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)