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1. (WO2019047336) SELF-ALIGNED TOP GATE ITZO THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREFOR
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Pub. No.: WO/2019/047336 International Application No.: PCT/CN2017/106778
Publication Date: 14.03.2019 International Filing Date: 19.10.2017
IPC:
H01L 29/786 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants:
华南理工大学 SOUTH CHINA UNIVERSITY OF TECHNOLOGY [CN/CN]; 中国广东省广州市 天河区五山路381号 No.381, Wushan Road, Tianhe District Guangzhou, Guangdong 510640, CN
Inventors:
陈荣盛 CHEN, Rongsheng; CN
邓孙斌 DENG, Sunbin; CN
郭海成 KWOK, Hoising; CN
Agent:
广州嘉权专利商标事务所有限公司 JIAQUAN IP LAW FIRM; 中国广东省广州市 天河区黄埔大道西100号富力盈泰广场A栋910张萍 ZHANG, Ping No.910, Building A, Winner Plaza, No.100, West Huangpu Avenue, Tianhe District Guangzhou, Guangdong 510627, CN
Priority Data:
201710792095.905.09.2017CN
Title (EN) SELF-ALIGNED TOP GATE ITZO THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREFOR
(FR) TRANSISTOR À COUCHES MINCES ITZO À GRILLE SUPÉRIEURE AUTO-ALIGNÉE ET SON PROCÉDÉ DE FABRICATION
(ZH) 一种自对准顶栅铟锡锌氧化物薄膜晶体管及其制造方法
Abstract:
(EN) Disclosed are a self-aligned top gate ITZO thin film transistor and a manufacturing method therefor. A transistor comprises a substrate, a buffer layer, an ITZO thin film, a gate dielectric layer, a conductive thin film, a passivation layer, source and drain contact electrodes and a gate electrode. The invention uses a self-aligned top gate structure to overcome the problem of traditional bottom gate transistors having a bigger parasitic capacitor and a weak capacity in scaling down at the same proportion, uses different gas sources and annealing conditions when depositing the passivation layer and the gate dielectric layer, such that the ITZO thin film region contacting and covered by the gate dielectric layer shows a high-impedance state, the ITZO thin film region contacting and covered by the passivation layer shows a low-impedance state, thereby forming a high-impedance groove region and a low-impedance source drain region, solving the problem in thermostability of traditional ion-doped metallic oxide thin film transistors. The present invention can be widely used in the field of semi-conductors.
(FR) L'invention concerne un transistor à couches minces ITZO à grille supérieure auto-alignée et son procédé de fabrication. Un transistor comprend un substrat, une couche tampon, un film mince ITZO, une couche diélectrique de grille, un film mince conducteur, une couche de passivation, des électrodes de contact de source et de drain et une électrode de grille. L'invention utilise une structure de grille supérieure auto-alignée pour surmonter le problème des transistors à grille inférieure classiques ayant un condensateur parasite plus grand et une capacité faible de mise à l'échelle à la même proportion, utilise différentes sources de gaz et conditions de recuit lors du dépôt de la couche de passivation et de la couche diélectrique de grille, de telle sorte que la région de film mince ITZO en contact et recouverte par la couche diélectrique de grille présente un état d'impédance élevée, la région de film mince ITZO en contact et recouverte par la couche de passivation présente un état de faible impédance, formant ainsi une région de rainure à impédance élevée et une région de drain de source à faible impédance, résolvant le problème de thermostabilité de transistors à couches minces d'oxyde métallique dopés aux ions classiques. La présente invention peut être largement utilisée dans le domaine des semi-conducteurs.
(ZH) 本发明公开了一种自对准顶栅铟锡锌氧化物薄膜晶体管及其制造方法,晶体管包括衬底、缓冲层、铟锡锌氧化物薄膜、栅介质层、导电薄膜、钝化层、源漏接触电极和栅电极。本发明采用了自对准顶栅结构,克服传统底栅型晶体管存在的寄生电容大和等比例缩小能力弱的问题,沉积钝化层和沉积栅介质层时使用不同的气源和退火条件,使得与栅介质层接触并被其覆盖的铟锡锌氧化物薄膜区域呈现高阻态,与钝化层接触并被其覆盖的铟锡锌氧化物薄膜区域呈现低阻态,从而形成形了高阻沟道区和低阻源漏区,解决了传统掺杂离子的金属氧化物薄膜晶体管的热稳定性问题。本发明可以广泛应用于半导体领域。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)