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1. (WO2019047329) LOW TEMPERATURE POLYCRYSTALLINE SILICON PANEL
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Pub. No.: WO/2019/047329 International Application No.: PCT/CN2017/105821
Publication Date: 14.03.2019 International Filing Date: 12.10.2017
IPC:
H01L 27/02 (2006.01) ,H01L 27/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
Applicants:
武汉华星光电技术有限公司 WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; 中国湖北省武汉市 东湖新技术开发区高新大道666号光谷生物创新园C5栋 Building C5, Biolake of Optics Valley No.666 Gaoxin Avenue, Wuhan East Lake High-tech Development Zone Wuhan, Hubei 430000, CN
Inventors:
韩约白 HAN, Yuebai; CN
Agent:
深圳汇智容达专利商标事务所(普通合伙) SHENZHEN RONDA PATENT AND TRADEMARK LAW OFFICE; 中国广东省深圳市 福田区深南中路求是大厦东座2709-2711 Unit 2709-2711 East Block, Qiushi Center Shennan Middle Road, Futian District Shenzhen, Guangdong 518040, CN
Priority Data:
201710791713.805.09.2017CN
Title (EN) LOW TEMPERATURE POLYCRYSTALLINE SILICON PANEL
(FR) PANNEAU DE SILICIUM POLYCRISTALLIN À BASSE TEMPÉRATURE
(ZH) 一种低温多晶硅面板
Abstract:
(EN) A low temperature polycrystalline silicon panel, said panel comprising an edge region; the edge region comprises: a polycrystalline silicon film layer (1) and an interlayer spacer layer (2) located above the polycrystalline silicon film layer (1); a row of virtual pixel units are provided on the interlayer spacer layer (2), a first conductive thin film layer (3) is provided above the row of virtual pixel units, the virtual pixels are insulated from the first conductive thin film layer (3) by means of a passivation layer (4); the row of virtual pixel units include a row of thin film transistors, and a data line electrically connected to the thin film transistors and used for accessing to a common signal; a first aperture (13) is provided on the interlayer spacer layer (2), and the polycrystalline silicon layer (1) is electrically connected to the data line through the first aperture (13). The low temperature polycrystalline silicon panel conducts away electric charges accumulating on the polycrystalline silicon layer (1), avoiding damage to the edge of the polycrystalline silicon panel due to burst, and preventing light leakage at the edge of the polycrystalline silicon panel.
(FR) L'invention concerne un panneau de silicium polycristallin à basse température, ledit panneau comprenant une zone de bord; la zone de bord comprend : une couche de pellicule (1) de silicium polycristallin et une couche d'entretoise intercouche (2) située au-dessus de la couche de pellicule (1) de silicium polycristallin; une ligne d'unités de pixels virtuels est disposée sur la couche d'entretoise intercouche (2), une première couche conductrice (3) à pellicule mince est disposée au-dessus de la ligne d'unités de pixels virtuels, les pixels virtuels sont isolés de la première couche conductrice (3) à pellicule mince au moyen d'une couche de passivation (4); la ligne d'unités de pixels virtuels inclut une ligne de transistors à couche mince, et une ligne de données connectée électriquement aux transistors à couche mince et servant à accéder à un signal commun; un premier orifice (13) est disposé sur la couche d'entretoise intercouche (2), et la couche de silicium polycristallin (1) est connectée électriquement à la ligne de données à travers le premier orifice (13). Le panneau de silicium polycristallin à basse température éloigne les charges électriques s'accumulant sur la couche de silicium polycristallin (1), évitant d'endommager le bord du panneau de silicium polycristallin par éclatement, et empêchant la fuite de lumière au bord du panneau de silicium polycristallin.
(ZH) 一种低温多晶硅面板,该面板包括边缘区域;边缘区域包括有:多晶硅膜层(1)以及位于多晶硅膜层(1)上方的层间间隔层(2);在层间间隔层(2)上设置有一列虚拟像素单元,在该列虚拟像素单元上方设置有第一导电薄膜层(3),虚拟像素单元与第一导电薄膜层(3)之间通过钝化层(4)绝缘隔开;该列虚拟像素单元包含有一列薄膜晶体管,以及与薄膜晶体管电性连接的用于接入公共信号的数据线;层间间隔层(2)上设置有第一开孔(13),多晶硅膜层(1)通过第一开孔(13)与数据线电性连接。所述低温多晶硅面板可以将多晶硅膜层(1)上聚集的电荷导走,避免多晶硅面板的边缘炸伤,还可以防止多晶硅面板边缘出现漏光。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)