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1. (WO2019047121) SUBSTRATE AND MANUFACTURING METHOD THEREFOR
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Pub. No.: WO/2019/047121 International Application No.: PCT/CN2017/100946
Publication Date: 14.03.2019 International Filing Date: 07.09.2017
IPC:
H01L 21/20 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
Applicants:
苏州晶湛半导体有限公司 ENKRIS SEMICONDUCTOR, INC. [CN/CN]; 中国江苏省苏州市 金鸡湖大道99号西北区20幢(NW-20幢)517-A室 Room 517-A Building NW-20, 99 Jinji Lake Avenue, Suzhou Industrial Park Suzhou, Jiangsu 215123, CN
Inventors:
张丽旸 ZHANG, Liyang; CN
程凯 CHENG, Kai; CN
Priority Data:
Title (EN) SUBSTRATE AND MANUFACTURING METHOD THEREFOR
(FR) SUBSTRAT ET PROCÉDÉ DE FABRICATION CORRESPONDANT
(ZH) 衬底及其制备方法
Abstract:
(EN) A substrate and a manufacturing method therefor, which relate to the field of semiconductors. The substrate comprises: a base substrate (10); a thin film layer (11), wherein the thin film layer (11) covers a part of a surface of the base substrate (10), causing the base substrate (10) to have an exposed surface (100) that is not covered by the thin film layer (11); and a recess (101), which is located on at least a part of the exposed surface (100). The substrate is provided with a recess, which may release stress that is produced due to lattice mismatch and thermal mismatch when an epitaxial layer grows on the substrate, thus reducing the risk of defects and cracks being produced due to overly high pressure, and reducing the warpage of a semiconductor that is subsequently prepared on the substrate so that the semiconductor has better quality and performance.
(FR) L'invention concerne un substrat et son procédé de fabrication, qui se rapportent au domaine des semi-conducteurs. Le substrat comprend : un substrat de base (10) ; une couche de film mince (11), la couche de film mince (11) recouvrant une partie d'une surface du substrat de base (10), amenant le substrat de base (10) à avoir une surface exposée (100) qui n'est pas recouverte par la couche de film mince (11) ; et un évidement (101), qui est situé sur au moins une partie de la surface exposée (100). Le substrat est pourvu d'un évidement, qui peut libérer une contrainte qui est produite en raison d'une désadaptation de réseau et d'une désadaptation thermique lorsqu'une couche épitaxiale croît sur le substrat, réduisant ainsi le risque de défauts et de fissures qui sont produits en raison d'une pression trop élevée, et réduisant le gauchissement d'un semi-conducteur qui est ensuite préparé sur le substrat de telle sorte que le semi-conducteur a une meilleure qualité et une meilleure performance.
(ZH) 一种衬底及其制备方法,属于半导体领域。衬底包括:基础衬底(10);薄膜层(11),其中所述薄膜层(11)覆盖部分所述基础衬底(10)的表面,使所述基础衬底(10)具有未被所述薄膜层(11)覆盖的裸露表面(100);以及凹孔(101),位于至少部分所述裸露表面(100)上。该衬底具有凹孔,可以释放当在衬底上生长外延层时由于晶格失配和热失配所产生的应力,降低因压力过大而导致产生缺陷和裂纹的风险,从而减小后续在该衬底上制备得到的半导体的翘曲度,使其具有更好的质量与性能。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)