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1. (WO2019047007) PACKAGE STRUCTURE OF SEMICONDUCTOR ELEMENT
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Pub. No.: WO/2019/047007 International Application No.: PCT/CN2017/100499
Publication Date: 14.03.2019 International Filing Date: 05.09.2017
IPC:
H01L 33/00 (2010.01) ,H01L 33/54 (2010.01) ,H01L 33/60 (2010.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
52
Encapsulations
54
having a particular shape
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
58
Optical field-shaping elements
60
Reflective elements
Applicants:
深圳前海小有技术有限公司 SHENZHEN QIANHAI XIAOYOU TECHNOLOGY CO., LTD. [CN/CN]; 中国广东省深圳市 前海深港合作区前湾一路1号A栋201室万永泉 WAN, Yong Quan Room 201, A Building No. 1 Qianwan 1st Road, Zone of Shenzhen-Hongkong Cooperation Shenzhen, Guangdong 518000, CN
深圳佑荟半导体有限公司 SHENZHEN UVEI SILICON CO., LTD. [CN/CN]; 中国广东省深圳市 福田区华富街道彩田路东方新天地广场C座2006-122万永泉 WAN, Yong Quan Room 2006-122, C Tower, Oriental Plaza Caitian Road, Huafu Street, Futian District Shenzhen, Guangdong 518000, CN
Inventors:
何宗江 HE, Zongjiang; CN
贾志强 JIA, Zhiqiang; CN
Agent:
深圳国新南方知识产权代理有限公司 SHENZHEN CHINA INNOVATION SOUTH INTELLECTUAL PROPERTY AGENCY CO., LTD.; 中国广东省深圳市 福田区深南大道1006号深圳国际创新中心C座22层陈艳欢 CHEN, Yan Huan 22F, Block C, Shenzhen International Innovation Center No. 1006 Shennan Road, Futian District Shenzhen, Guangdong 518000, CN
Priority Data:
Title (EN) PACKAGE STRUCTURE OF SEMICONDUCTOR ELEMENT
(FR) STRUCTURE DE BOÎTIER D’ÉLÉMENT SEMI-CONDUCTEUR
(ZH) 半导体元件的封装结构
Abstract:
(EN) A package structure of a semiconductor element, comprising: a substrate (101), an insulating glue layer (104) disposed on a lower surface of the substrate, a chip (105) disposed on an upper surface of the substrate (101), a reflector cup (106) and transmitting cover (107), and an electrode (103) leading out from a lower surface of the chip (105), penetrating the substrate (101) and extending into the insulating glue layer (104), wherein the transmitting cover (107) is fastened on the substrate (101) so as to cover an upper surface of the substrate (101) and sealingly bond to the substrate (101). The waterproofing and sealing nature of the package structure is greatly improved by means of the arrangement of the transmitting cover (107) and the underlying insulating glue layer (104), the seal bonding between the transmitting cover (107) and the substrate (101), and the design of a seal layer blocking off the external environment that is obtained by using the gluing function of sealants or by generating a metal eutectic. Meanwhile, the design of a concentrating column and various supporting structures achieves excellent stability and compressive performance of the package structure, so that the package structure is very suitable for harsh environments such as a high pressure and high humidity underwater environment.
(FR) L'invention concerne une structure de boîtier d'un élément semi-conducteur, comprenant : un substrat (101), une couche de colle isolante (104) disposée sur une surface inférieure du substrat, une puce (105) disposée sur une surface supérieure du substrat (101), une coupelle réflectrice (106) et un couvercle de transmission (107), et une électrode (103) sortant d'une surface inférieure de la puce (105), pénétrant dans le substrat (101) et s'étendant dans la couche de colle isolante (104), le couvercle de transmission (107) étant fixé sur le substrat (101) de manière à recouvrir une surface supérieure du substrat (101) et se liant de manière étanche au substrat (101). L'imperméabilité et la nature d'étanchéité de la structure de boîtier sont considérablement améliorées au moyen de l'agencement du couvercle de transmission (107) et de la couche de colle isolante sous-jacente (104), de la liaison étanche entre le couvercle de transmission (107) et le substrat (101), et de la conception d'une couche d'étanchéité bloquant l'environnement externe qui est obtenue en utilisant la fonction de collage de produits d'étanchéité ou en générant un eutectique métallique. Parallèlement, la conception d'une colonne de concentration et de diverses structures de support permet d'obtenir une excellente stabilité et une excellente performance de compression de la structure de boîtier, de telle sorte que la structure de boîtier est très appropriée pour des environnements hostiles tels qu'un environnement sous-marin à haute pression et humidité élevée.
(ZH) 一种半导体元件的封装结构,包括:基板(101)、设置在基板下表面的绝缘胶层(104)、设置在基板(101)上表面的芯片(105)、反光杯(106)和透光罩(107),以及从芯片(105)的下表面引出并穿过所述基板(101)延伸至绝缘胶层(104)中的电极(103),其中透光罩(107)扣设于基板(101)上以覆盖基板(101)的上表面,并以密封的方式与基板(101)粘接。通过透光罩(107)和底层绝缘胶层(104)的设置,并使得透光罩(107)与基板(101)密封粘接,通过密封胶的胶粘或者通过生成金属共晶体,以及隔绝外界环境的密封层的设计,极大地提高了封装结构的防水密封性,同时通过聚光柱以及各种支撑结构的设计,使得封装结构的稳定性能和抗压性能优异,非常适合于高压高湿的水下等恶劣环境。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)