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1. (WO2019046745) INTEGRATED CIRCUIT PACKAGE WITH STRESS DIRECTING MATERIAL
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Pub. No.: WO/2019/046745 International Application No.: PCT/US2018/049135
Publication Date: 07.03.2019 International Filing Date: 31.08.2018
IPC:
H01L 21/56 (2006.01) ,H01L 23/28 (2006.01) ,H01L 27/04 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56
Encapsulations, e.g. encapsulating layers, coatings
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
Applicants:
TEXAS INSTRUMENTS INCORPORATED [US/US]; P.O. Box 655474 Mail Station 3999 Dallas, TX 75265-5474, US
TEXAS INSTRUMENTS JAPAN LIMITED [JP/JP]; 24-1, Nishi-Shinjuku 6-chome Shinjuku-ku Tokyo 160-8366, JP (JP)
Inventors:
COOK, Benjamin Stassen; US
REVIER, Daniel Lee; US
Agent:
DAVIS, Micheal A. Jr.; US
Priority Data:
15/693,36831.08.2017US
Title (EN) INTEGRATED CIRCUIT PACKAGE WITH STRESS DIRECTING MATERIAL
(FR) BOÎTIER DE CIRCUIT INTÉGRÉ AVEC MATÉRIAU DE RÉPARTITION DES CONTRAINTES
Abstract:
(EN) An encapsulated integrated circuit (100) includes an integrated circuit (IC) die (102) and an encapsulation material (110) encapsulating the IC die (102). A first portion of the encapsulation material (110) is solid, and a second portion (120) of the encapsulation material (110) includes spaces filled with a second material.
(FR) Cette invention concerne un circuit intégré encapsulé (100) comprenant une puce (102) de circuit intégré (CI) et un matériau d'encapsulation (110) encapsulant la puce de CI (102). Une première partie du matériau d'encapsulation (110) est solide, et une seconde partie (120) du matériau d'encapsulation (110) comprend des espaces remplis d'un second matériau.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)