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1. (WO2019046723) IMPLICIT GLOBAL POINTER RELATIVE ADDRESSING FOR GLOBAL MEMORY ACCESS
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Pub. No.: WO/2019/046723 International Application No.: PCT/US2018/049099
Publication Date: 07.03.2019 International Filing Date: 31.08.2018
IPC:
G06F 9/30 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
Applicants:
MIPS TECH, LLC [US/US]; 3201 Scott Blvd. Santa Clara, CA 95054, US
Inventors:
ROBINSON, James, Hippisley; US
TAYLOR, Morgyn; US
FORTUNE, Matthew; GB
FUHLER, Richard; US
PATEL, Sanjay; US
Agent:
ADAMS, R., Dean; US
Priority Data:
62/552,85531.08.2017US
Title (EN) IMPLICIT GLOBAL POINTER RELATIVE ADDRESSING FOR GLOBAL MEMORY ACCESS
(FR) ADRESSAGE RELATIF DE POINTEUR GLOBAL IMPLICITE POUR ACCÈS À LA MÉMOIRE GLOBALE
Abstract:
(EN) Instruction set architectures (ISAs) and apparatus and methods related thereto comprise an instruction set that includes one or more instructions which identify the global pointer (GP) register as an operand (e.g., base register or source register) of the instruction. Identification can be implicit. By implicitly identifying the GP register as an operand of the instruction, one or more bits of the instruction that were dedicated to explicitly identifying the operand (e.g., base register or source register) can be used to extend the size of one or more other operands, such as the offset or immediate, to provide longer offsets or immediates.
(FR) L'invention concerne des architectures de jeu d'instructions (ISA) et un appareil et des procédés associés qui comportent un jeu d'instructions qui comprend une ou plusieurs instructions qui identifient le registre de pointeur global (GP) en tant qu'opérande (par exemple, registre de base ou registre source) de l'instruction. L'identification peut être implicite. Par identification implicite du registre GP en tant qu'opérande de l'instruction, un ou plusieurs bits de l'instruction qui ont été réservés à l'identification explicite de l'opérande (par exemple, registre de base ou registre source) peuvent être utilisés pour étendre la taille d'un ou de plusieurs autres opérandes, tels que l'opérande de décalage ou l'opérande immédiat, pour fournir des opérandes de décalage ou des opérandes immédiats plus longs.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)